Expand description
Registers of the DRS4 are accessed through the sytem ram (Addr8). It is a 32bit system, so the address format is u32. _ a note here _ : Each register is 32bit. This means for the Addr8 (8 refers to bits) a register occupies 4 bytes, so a new register will be the previous register + 4. If the register is the same as another, then the register holds different fields for the different bits in the register.
Constantsยง
- ADC_
LATENCY - BOARD_
ID - BUSY
- CNT_
DMA_ READOUTS_ COMPLETED - CNT_
EVENT - CNT_
LOST_ EVENT - CNT_
READOUTS_ COMPLETED - CNT_
RESET - CNT_
SEM_ CORRECTION - DRS counters
- CNT_
SEM_ UNCORRECTABLE - DAQ_
BUSY - DAQ_
RESET - DMA_
CLEAR - DMA_
POINTER - DMA_
RESET - DNA_
LSBS - Device DNA (identifier) it is split in 2 32-bit words, since the whole thing is 64 bit
- DNA_
MSBS - DRS_
CONFIGURE - DRS_
DEADTIME - DRS_DEADTIME 0x1e 0x78 [15:0] r Measured last deadtime of the DRS in clock cycles
- DRS_
REINIT - DRS_
RESET - DRS_
START - EN_
SPIKE_ REMOVAL - FORCE_
TRIG - LOST_
TRIGGER_ RATE - MT_
EVENT_ CNT - MT_
LINK_ ID - MT_
TRIGGER_ MODE - DRS trigger
- MT_
TRIG_ RATE - RAM_
A_ OCCUPANCY - RAM_
A_ OCC_ RST - RAM management - there are two regions in memory, mapped to /dev/uio1 and /dev/uio2 which hold the blob data, denoted as ram buffers a and b
- RAM_
B_ OCCUPANCY - RAM_
B_ OCC_ RST - READOUT_
MASK - ROI_
MODE - SAMPLE_
COUNT - SOFT_
RESET - SOFT_
RESET_ DONE - TOGGLE_
RAM - TRIGGER_
ENABLE - TRIGGER_
RATE - TRIG_
GEN_ RATE - WRITE_
EVENTFRAGMENT