liftof_rb/registers.rs
1//! Registers of the DRS4 are accessed through
2//! the sytem ram (Addr8). It is a 32bit system,
3//! so the address format is u32.
4//! _ a note here _ : Each register is 32bit. This means for
5//! the Addr8 (8 refers to bits) a register occupies 4 bytes,
6//! so a new register will be the previous register + 4.
7//! If the register is the same as another, then the register
8//! holds different fields for the different bits in the register.
9//!
10//! [For the latest version of the registers, please refer to]([https://gitlab.com/ucla-gaps-tof/firmware/-/blob/develop/regmap/rb_address_table.org)
11
12//========== DRS4 Registers =============
13//
14//=======================================
15
16pub const ROI_MODE : u32 = 0x40; //00x1 Set to 1 to enable Region of Interest Readout
17pub const BUSY : u32 = 0x40; //1 DRS is busy
18pub const ADC_LATENCY : u32 = 0x40; //[9:4] rw 0x9 Latency from first sr clock to when ADC data should be valid
19pub const SAMPLE_COUNT : u32 = 0x40; //[21:12] rw 0x3FF Number of samples to read out (0 to 1023)
20pub const EN_SPIKE_REMOVAL : u32 = 0x40; //22 rw 0x1 set 1 to enable spike removal
21
22pub const FORCE_TRIG : u32 = 0x100; // Write 1 to set forced trigger mode
23
24pub const DRS_CONFIGURE : u32 = 0x50; // Write 1 to configure the DRS. Should be done before data taking
25pub const DRS_START : u32 = 0x48; // Write 1 to take the state machine out of idle mode
26pub const DRS_REINIT : u32 = 0x4c; // Write 1 to reinitialize DRS state machine (restores to idle state)
27
28pub const DMA_CLEAR : u32 = 0x6c; // [0] Write 1 to clear the DMA memory (write zeroes)
29
30pub const DRS_RESET : u32 = 0x54; // WRite 1 to completely reset the DRS state machine logic
31pub const DAQ_RESET : u32 = 0x58; // Write 1 to completely reset the DAQ state machine logic
32pub const DMA_RESET : u32 = 0x5c; // Write 1 to completely reset the DMA state machine logic
33
34// channel mask is 8 bit, the register contains also
35// the channel 9 auto bit mask
36pub const READOUT_MASK : u32 = 0x44; // [8:0] 8 bit mask, set a bit to 1 to enable readout of that channel.
37 // 9th is auto-read if any channel is enabled and AUTO_9TH_CHANNEL set to 1
38
39pub const TRIGGER_ENABLE : u32 = 0x11c; // Write 0 to stop all triggers, 1 to enable triggering
40
41pub const WRITE_EVENTFRAGMENT : u32 = 0xc4;
42pub const TRIG_GEN_RATE : u32 = 0x164;
43
44// this is at bit 1, where WRITE_EVENTFRAGMENT technically
45// is only at bit 0. Have 2 seperate addresses to not
46// be confusing in th control functions.
47pub const DAQ_BUSY : u32 = 0xc4;
48
49//=================DMA==================================
50// (direct memory access)
51//======================================================
52
53/// RAM management - there are two regions in memory, mapped
54/// to /dev/uio1 and /dev/uio2 which hold the blob data,
55/// denoted as ram buffers a and b
56pub const RAM_A_OCC_RST :u32 = 0x400;//[0] Sets RAM buffer a counter to 0
57pub const RAM_B_OCC_RST :u32 = 0x404;//[0] Sets RAM buffer b counter to 0
58pub const RAM_A_OCCUPANCY :u32 = 0x408;//[31:0] RAM buffer a occupancy
59pub const RAM_B_OCCUPANCY :u32 = 0x40c;//[31:0] RAM buffer b occupancy
60pub const DMA_POINTER :u32 = 0x410;//[31:0] DMA controller pointer
61pub const TOGGLE_RAM :u32 = 0x414;//[0] Write 1 to switch the dma buffer to the other half
62
63/// DRS trigger
64pub const MT_TRIGGER_MODE : u32 = 0x114; //1 to use the MT as the source of the trigger
65
66
67/// DRS counters
68
69pub const CNT_SEM_CORRECTION : u32 = 0x140; //[15:0] Number of Single Event Errors corrected by the scrubber
70pub const CNT_SEM_UNCORRECTABLE : u32 = 0x144; //[19:16] Number of Critical Single Event Errors (uncorrectable by scrubber)
71pub const CNT_READOUTS_COMPLETED : u32 = 0x148; // [31:0] Number of readouts completed since reset
72pub const CNT_DMA_READOUTS_COMPLETED : u32 = 0x14c; //[31:0] Number of readouts completed since reset
73pub const CNT_LOST_EVENT : u32 = 0x150; //[31:16] Number of trigger lost due to deadtime
74pub const CNT_EVENT : u32 = 0x154; //[31:0] Number of triggers received
75pub const TRIGGER_RATE : u32 = 0x158; //[31:0] Rate of triggers in Hz
76pub const LOST_TRIGGER_RATE : u32 = 0x15c; //[31:0]Rate of lost triggers in Hz
77pub const CNT_RESET : u32 = 0x160; //[0]Reset the counters
78
79/// Device DNA (identifier)
80/// it is split in 2 32-bit words, since the whole
81/// thing is 64 bit
82pub const DNA_LSBS : u32 = 0x80; //[31:0] Device DNA [31:0]
83pub const DNA_MSBS : u32 = 0x84; //[24:0] Device DNA [56:32]
84
85// FPGA
86pub const BOARD_ID : u32 = 0xa8; //[7:0] Board ID Number
87
88// SOFT RESET
89pub const SOFT_RESET : u32 = 0x70;
90pub const SOFT_RESET_DONE : u32 = 0x74;
91
92// MT EVENT REGISTERS
93pub const MT_EVENT_CNT : u32 = 0x120;
94pub const MT_TRIG_RATE : u32 = 0x124;
95pub const MT_LINK_ID : u32 = 0x104;
96
97
98// RB DEADTIME
99//
100//
101///DRS_DEADTIME 0x1e 0x78 \[15:0\] r Measured last deadtime of the DRS in clock cycles
102pub const DRS_DEADTIME : u32 = 0x78;