tof_control/rb_control/
rb_vcp.rs1use crate::constant::*;
2use crate::helper::rb_type::{RBVcp, RBError};
3use crate::device::{ina226, max11645, pca9548a};
4
5impl RBVcp {
6 pub fn new() -> Self {
7 match Self::read_vcp() {
8 Ok(rb_vcp) => {
9 rb_vcp
10 }
11 Err(_) => {
12 Self {
13 zynq_vcp: [f32::MAX; 3],
14 p3v3_vcp: [f32::MAX; 3],
15 p3v5_vcp: [f32::MAX; 3],
16 n1v5_vcp: [f32::MAX; 3],
17 drs_dvdd_vcp: [f32::MAX; 3],
18 drs_avdd_vcp: [f32::MAX; 3],
19 adc_dvdd_vcp: [f32::MAX; 3],
20 adc_avdd_vcp: [f32::MAX; 3],
21 }
22 }
23 }
24 }
25 pub fn read_vcp() -> Result<RBVcp, RBError> {
26 let i2c_mux_1 = pca9548a::PCA9548A::new(I2C_BUS, RB_PCA9548A_ADDRESS_1);
27 let i2c_mux_2 = pca9548a::PCA9548A::new(I2C_BUS, RB_PCA9548A_ADDRESS_2);
28
29 i2c_mux_1.select(RB_ZYNQ_INA226_CHANNEL)?;
30 let zynq_ina226 = ina226::INA226::new(I2C_BUS, RB_ZYNQ_INA226_ADDRESS, RB_ZYNQ_INA226_RSHUNT, RB_ZYNQ_INA226_MEC,);
31 zynq_ina226.configure()?;
32 let zynq_vcp = zynq_ina226.read()?;
33
34 i2c_mux_1.select(RB_P3V3_INA226_CHANNEL)?;
35 let p3v3_ina226 = ina226::INA226::new(I2C_BUS, RB_P3V3_INA226_ADDRESS, RB_P3V3_INA226_RSHUNT, RB_P3V3_INA226_MEC);
36 p3v3_ina226.configure()?;
37 let p3v3_vcp =p3v3_ina226.read()?;
38
39 i2c_mux_1.select(RB_P3V5_INA226_CHANNEL)?;
40 let p3v5_ina226 = ina226::INA226::new(I2C_BUS, RB_P3V5_INA226_ADDRESS, RB_P3V5_INA226_RSHUNT, RB_P3V5_INA226_MEC);
41 p3v5_ina226.configure()?;
42 let p3v5_vcp = p3v5_ina226.read()?;
43
44 i2c_mux_1.select(RB_MAX11645_CHANNEL)?;
45 let max11645 = max11645::MAX11645::new(I2C_BUS, RB_MAX11645_ADDRESS);
46 max11645.setup()?;
47 let n1v5_voltage = max11645.read(RB_N1V5_VOLTAGE_INA200_CHANNEL)? * -1.0;
48 let n1v5_current = max11645.read(RB_N1V5_CURRENT_INA200_CHANNEL)? / 20.0 / 0.039;
49 let n1v5_power = n1v5_voltage.abs() * n1v5_current;
50 let n1v5_vcp = [n1v5_voltage, n1v5_current, n1v5_power];
51
52 i2c_mux_1.select(RB_DRS_DVDD_INA226_CHANNEL)?;
53 let drs_dvdd_ina226 = ina226::INA226::new(I2C_BUS, RB_DRS_DVDD_INA226_ADDRESS, RB_DRS_DVDD_INA226_RSHUNT, RB_DRS_DVDD_INA226_MEC);
54 drs_dvdd_ina226.configure()?;
55 let drs_dvdd_vcp = drs_dvdd_ina226.read()?;
56
57 i2c_mux_2.select(RB_DRS_AVDD_INA226_CHANNEL)?;
58 let drs_avdd_ina226 = ina226::INA226::new(I2C_BUS, RB_DRS_AVDD_INA226_ADDRESS, RB_DRS_AVDD_INA226_RSHUNT, RB_DRS_AVDD_INA226_MEC);
59 drs_avdd_ina226.configure()?;
60 let drs_avdd_vcp = drs_avdd_ina226.read()?;
61
62 i2c_mux_2.select(RB_ADC_DVDD_INA226_CHANNEL)?;
63 let adc_dvdd_ina226 = ina226::INA226::new(I2C_BUS, RB_ADC_DVDD_INA226_ADDRESS, RB_ADC_DVDD_INA226_RSHUNT, RB_ADC_DVDD_INA226_MEC);
64 adc_dvdd_ina226.configure()?;
65 let adc_dvdd_vcp = adc_dvdd_ina226.read()?;
66
67 i2c_mux_2.select(RB_ADC_AVDD_INA226_CHANNEL)?;
68 let adc_avdd_ina226 = ina226::INA226::new(I2C_BUS, RB_ADC_AVDD_INA226_ADDRESS, RB_ADC_AVDD_INA226_RSHUNT, RB_ADC_AVDD_INA226_MEC);
69 adc_avdd_ina226.configure()?;
70 let adc_avdd_vcp = adc_avdd_ina226.read()?;
71
72 i2c_mux_1.reset()?;
73 i2c_mux_2.reset()?;
74
75 Ok(
76 RBVcp {
77 zynq_vcp,
78 p3v3_vcp,
79 p3v5_vcp,
80 n1v5_vcp,
81 drs_dvdd_vcp,
82 drs_avdd_vcp,
83 adc_dvdd_vcp,
84 adc_avdd_vcp,
85 }
86 )
87
88 }
89}
90
91pub fn config_vcp() -> Result<(), RBError> {
92 let i2c_mux_1 = pca9548a::PCA9548A::new(I2C_BUS, RB_PCA9548A_ADDRESS_1);
93 let i2c_mux_2 = pca9548a::PCA9548A::new(I2C_BUS, RB_PCA9548A_ADDRESS_2);
94
95 i2c_mux_1.select(RB_DRS_DVDD_INA226_CHANNEL)?;
96 let drs_dvdd_ina226 = ina226::INA226::new(
97 I2C_BUS,
98 RB_DRS_DVDD_INA226_ADDRESS,
99 RB_DRS_DVDD_INA226_RSHUNT,
100 RB_DRS_DVDD_INA226_MEC,
101 );
102 for _ in 0..3 {
103 drs_dvdd_ina226.configure()?;
104 drs_dvdd_ina226.read()?;
105 }
106
107 i2c_mux_1.select(RB_P3V3_INA226_CHANNEL)?;
108 let p3v3_ina226 = ina226::INA226::new(
109 I2C_BUS,
110 RB_P3V3_INA226_ADDRESS,
111 RB_P3V3_INA226_RSHUNT,
112 RB_P3V3_INA226_MEC,
113 );
114 for _ in 0..3 {
115 p3v3_ina226.configure()?;
116 p3v3_ina226.read()?;
117 }
118
119 i2c_mux_1.select(RB_ZYNQ_INA226_CHANNEL)?;
120 let zynq_ina226 = ina226::INA226::new(
121 I2C_BUS,
122 RB_ZYNQ_INA226_ADDRESS,
123 RB_ZYNQ_INA226_RSHUNT,
124 RB_ZYNQ_INA226_MEC,
125 );
126 zynq_ina226.configure()?;
127 zynq_ina226.read()?;
128 zynq_ina226.read()?;
129
130 i2c_mux_1.select(RB_P3V5_INA226_CHANNEL)?;
131 let p3v5_ina226 = ina226::INA226::new(
132 I2C_BUS,
133 RB_P3V5_INA226_ADDRESS,
134 RB_P3V5_INA226_RSHUNT,
135 RB_P3V5_INA226_MEC,
136 );
137 for _ in 0..3 {
138 p3v5_ina226.configure()?;
139 p3v5_ina226.read()?;
140 }
141
142 i2c_mux_2.select(RB_ADC_DVDD_INA226_CHANNEL)?;
143 let adc_dvdd_ina226 = ina226::INA226::new(
144 I2C_BUS,
145 RB_ADC_DVDD_INA226_ADDRESS,
146 RB_ADC_DVDD_INA226_RSHUNT,
147 RB_ADC_DVDD_INA226_MEC,
148 );
149 for _ in 0..3 {
150 adc_dvdd_ina226.configure()?;
151 adc_dvdd_ina226.read()?;
152 }
153
154 i2c_mux_2.select(RB_ADC_AVDD_INA226_CHANNEL)?;
155 let adc_avdd_ina226 = ina226::INA226::new(
156 I2C_BUS,
157 RB_ADC_AVDD_INA226_ADDRESS,
158 RB_ADC_AVDD_INA226_RSHUNT,
159 RB_ADC_AVDD_INA226_MEC,
160 );
161 for _ in 0..3 {
162 adc_avdd_ina226.configure()?;
163 adc_avdd_ina226.read()?;
164 }
165
166 i2c_mux_2.select(RB_DRS_AVDD_INA226_CHANNEL)?;
167 let drs_avdd_ina226 = ina226::INA226::new(
168 I2C_BUS,
169 RB_DRS_AVDD_INA226_ADDRESS,
170 RB_DRS_AVDD_INA226_RSHUNT,
171 RB_DRS_AVDD_INA226_MEC,
172 );
173 for _ in 0..3 {
174 drs_avdd_ina226.configure()?;
175 drs_avdd_ina226.read()?;
176 }
177
178 i2c_mux_1.select(RB_MAX11645_CHANNEL)?;
179 let max11645 = max11645::MAX11645::new(I2C_BUS, RB_MAX11645_ADDRESS);
180 max11645.setup()?;
181
182 i2c_mux_1.reset()?;
183 i2c_mux_2.reset()?;
184
185 Ok(())
186}