tof_control/
constant.rs

1#![allow(unused)]
2// I2C Options
3pub const I2C_BUS: u8 = 0;
4
5// I2C Options for Readout Board
6pub const RB_PCA9548A_ADDRESS_1: u16 = 0x75;
7pub const RB_PCA9548A_ADDRESS_2: u16 = 0x77;
8
9// PCA9548A_ADDRESS_1
10pub const RB_DRS_TMP112_ADDRESS: u16 = 0x48;
11pub const RB_DRS_TMP112_CHANNEL: u8 = 2;
12// PCA9548A_ADDRESS_2
13pub const RB_CLK_TMP112_ADDRESS: u16 = 0x4B;
14pub const RB_CLK_TMP112_CHANNEL: u8 = 0;
15pub const RB_ADC_TMP112_ADDRESS: u16 = 0x4A;
16pub const RB_ADC_TMP112_CHANNEL: u8 = 4;
17
18// PCA9548A_ADDRESS_1
19pub const RB_DRS_DVDD_INA226_ADDRESS: u16 = 0x4E;
20pub const RB_DRS_DVDD_INA226_CHANNEL: u8 = 3;
21pub const RB_DRS_DVDD_INA226_RSHUNT: f32 = 0.1;
22pub const RB_DRS_DVDD_INA226_MEC: f32 = 0.1;
23
24pub const RB_P3V3_INA226_ADDRESS: u16 = 0x44;
25pub const RB_P3V3_INA226_CHANNEL: u8 = 4;
26pub const RB_P3V3_INA226_RSHUNT: f32 = 0.039;
27pub const RB_P3V3_INA226_MEC: f32 = 0.75;
28
29pub const RB_ZYNQ_INA226_ADDRESS: u16 = 0x41;
30pub const RB_ZYNQ_INA226_CHANNEL: u8 = 5;
31pub const RB_ZYNQ_INA226_RSHUNT: f32 = 0.039;
32pub const RB_ZYNQ_INA226_MEC: f32 = 0.75;
33
34pub const RB_P3V5_INA226_ADDRESS: u16 = 0x43;
35pub const RB_P3V5_INA226_CHANNEL: u8 = 7;
36pub const RB_P3V5_INA226_RSHUNT: f32 = 0.039;
37pub const RB_P3V5_INA226_MEC: f32 = 0.75;
38
39// PCA9548A_ADDRESS_2
40pub const RB_ADC_DVDD_INA226_ADDRESS: u16 = 0x42;
41pub const RB_ADC_DVDD_INA226_CHANNEL: u8 = 3;
42pub const RB_ADC_DVDD_INA226_RSHUNT: f32 = 0.1;
43pub const RB_ADC_DVDD_INA226_MEC: f32 = 0.01;
44
45pub const RB_ADC_AVDD_INA226_ADDRESS: u16 = 0x4F;
46pub const RB_ADC_AVDD_INA226_CHANNEL: u8 = 5;
47pub const RB_ADC_AVDD_INA226_RSHUNT: f32 = 0.1;
48pub const RB_ADC_AVDD_INA226_MEC: f32 = 0.075;
49
50pub const RB_DRS_AVDD_INA226_ADDRESS: u16 = 0x40;
51pub const RB_DRS_AVDD_INA226_CHANNEL: u8 = 6;
52pub const RB_DRS_AVDD_INA226_RSHUNT: f32 = 0.1;
53pub const RB_DRS_AVDD_INA226_MEC: f32 = 0.025;
54
55// PCA9548A_ADDRESS_1
56pub const RB_LIS3MDLTR_ADDRESS: u16 = 0x1E;
57pub const RB_LIS3MDLTR_CHANNEL: u8 = 1;
58
59// PCA9548A_ADDRESS_1
60pub const RB_BME280_ADDRESS: u16 = 0x76;
61pub const RB_BME280_CHANNEL: u8 = 0;
62
63// PCA9548A_ADDRESS_1
64pub const RB_ADC_REF_VOLTAGE: f32 = 2.048;
65pub const RB_MAX11645_ADDRESS: u16 = 0x36;
66pub const RB_MAX11645_CHANNEL: u8 = 6;
67
68pub const RB_N1V5_VOLTAGE_INA200_CHANNEL: u8 = 1;
69pub const RB_N1V5_CURRENT_INA200_CHANNEL: u8 = 0;
70
71// Clock Synthesizer (SI5345B)
72// PCA9548A_ADDRESS_2
73pub const RB_SI5345B_ADDRESS: u16 = 0x68;
74pub const RB_SI5345B_CHANNEL: u8 = 1;
75
76// GPIO Expander (CY8C9560A)
77// PCA9548A_ADDRESS_2
78pub const RB_CY8C9560A_ADDRESS: u16 = 0x20;
79pub const RB_CY8C9560A_EEPROM_ADDRESS: u16 = 0x50;
80pub const RB_CY8C9560A_CHANNEL: u8 = 7;
81
82/// DAC (AD5675)
83// PCA9548A_ADDRESS_2
84pub const RB_AD5675_ADDRESS: u16 = 0xC;
85pub const RB_AD5675_CHANNEL: u8 = 2;
86
87/// RB Internal Address Table
88pub const RB_UIO0: &'static str = "/dev/uio0";
89
90/// DRS.CHIP (Registers for configuring the DRS ASIC Directly)
91pub const DRS_PLL_LOCK: u32 = 0x00; // Bits: 4, Perm: r, Description: DRS PLL Locked
92pub const LOSS_OF_LOCK: u32 = 0x10; // Bits: 0, Perm: r, Description: Raw reading of LOL signal
93pub const LOSS_OF_LOCK_STABLE: u32 = 0x10; // Bits: 1, Perm: r, Description: Loss of lock stable over the past ~second
94/// DRS.FPGA.XADC (Zynq XADC)
95pub const RB_TEMP: u32 = 0xA0; // Bits: [11:0], Perm: r, XADC Temperature
96/// DRS.FPGA (FPGA Status)
97pub const BOARD_ID: u32 = 0xA8; // Bits: [7:0], Perm: rw, Board ID Number
98pub const DRS_TEMP: u32 = 0xAC; // Bits: [15:0], Perm: rw, Copy of the I2C DRS temperature reading
99pub const RAT_HOUSEKEEPING: u32 = 0xB0; // Bits: [31:0], Perm: rw, 32 bit RAT housekeeping data. Meaning is software defined.
100/// DRS.DAQ (DAQ)
101pub const DAQ_FRAGMENT_EN: u32 = 0xC4; // Bits: 0, Perm: rw, 1 to enable daq fragments (header only packets) when the DRS is busy
102/// DRS.READOUT (Registers for configuring the readout state machine)
103pub const EN_SPIKE_REMOVAL: u32 = 0x40; // Bits: 22, Perm: rw, Description: set 1 to enable spike removal
104pub const READOUT_MASK: u32 = 0x44; // Bits: [8:0], Perm: rw, 8 bit mask, set a bit to 1 to enable readout of that channel. 9th is auto-read if any channel is enabled and AUTO_9TH_CHANNEL set to 1
105pub const START: u32 = 0x48; // Bits: 0, Perm: w, Description: Write 1 to take the state machine out of idle mode
106/// DRS.TRIGGER
107pub const TRIGGER_ENABLE: u32 = 0x11C; // Bits: 0, Perm: rw, Description: Set to 0 to stop all triggers. 1 to enable triggers.
108pub const MT_EVENT_CNT: u32 = 0x120; // Bits: [31:0], Perm: r, Description: Recevied event counter
109pub const MT_TRIGGER_RATE: u32 = 0x124; // Bits: [31:0], Perm: r, Description: Rate of triggers received from the MTB in Hz
110/// DRS.COUNTERS
111pub const CNT_LOST_EVENT: u32 = 0x150; // Bits: [31:16], Perm: r, Description: Number of trigger lost due to deadtime
112pub const CNT_EVENT: u32 = 0x154; // Bits: [31:0], Perm: r, Description: Number of triggers received
113pub const TRIGGER_RATE: u32 = 0x158; // Bits: [31:0], Perm: r, Description: Rate of triggers in Hz
114pub const LOST_TRIGGER_RATE: u32 = 0x15C; // Bits: [31:0], Perm: r, Description: Rate of lost triggers in Hz
115/// DRS.HOG (HOG Parameters)
116pub const GLOBAL_VER: u32 = 0x188; // Bits: [31:0], Perm: r, Description: HOG Global Version
117pub const GLOBAL_SHA: u32 = 0x18C; // Bits: [31:0], Perm: r, Description: HOG Global SHA
118
119// I2C Options for Power Board
120pub const PB_PCA9548A_ADDRESS: u16 = 0x70;
121
122pub const PB_TMP1075_CHANNEL: u8 = 4;
123pub const PB_PDS_TMP1075_ADDRESS: u16 = 0x48;
124pub const PB_PAS_TMP1075_ADDRESS: u16 = 0x49;
125pub const PB_NAS_TMP1075_ADDRESS: u16 = 0x4A;
126pub const PB_SHV_TMP1075_ADDRESS: u16 = 0x4B;
127
128pub const PB_P3V6_PA_INA226_ADDRESS: u16 = 0x46;
129pub const PB_P3V6_PA_INA226_CHANNEL: u8 = 6;
130pub const PB_P3V6_PA_INA226_RSHUNT: f32 = 0.1;
131pub const PB_P3V6_PA_INA226_MEC: f32 = 0.35;
132pub const PB_N1V6_PA_VOLTAGE_INA201_CHANNEL: u8 = 3;
133pub const PB_N1V6_PA_CURRENT_INA201_CHANNEL: u8 = 2;
134pub const PB_LTB_INA219_CHANNEL: u8 = 5;
135pub const PB_P3V4F_LTB_INA219_ADDRESS: u16 = 0x46;
136pub const PB_P3V4F_LTB_INA219_RSHUNT: f32 = 0.1;
137pub const PB_P3V4F_LTB_INA219_MEC: f32 = 0.05;
138pub const PB_P3V4D_LTB_INA219_ADDRESS: u16 = 0x47;
139pub const PB_P3V4D_LTB_INA219_RSHUNT: f32 = 0.1;
140pub const PB_P3V4D_LTB_INA219_MEC: f32 = 0.075;
141pub const PB_P3V6_LTB_INA219_ADDRESS: u16 = 0x4C;
142pub const PB_P3V6_LTB_INA219_RSHUNT: f32 = 0.1;
143pub const PB_P3V6_LTB_INA219_MEC: f32 = 0.25;
144pub const PB_N1V6_LTB_VOLTAGE_INA202_CHANNEL: u8 = 3;
145pub const PB_N1V6_LTB_CURRENT_INA202_CHANNEL: u8 = 2;
146
147pub const PB_ADC_REF_VOLTAGE: f32 = 3.0;
148pub const PB_ADC_1_CHANNEL: u8 = 1;
149pub const PB_ADC_2_CHANNEL: u8 = 3;
150pub const PB_MAX11615_ADDRESS: u16 = 0x33;
151pub const PB_MAX11617_ADDRESS: u16 = 0x35;
152
153pub const PB_DAC_REF_VOLTAGE: f32 = 3.0;
154pub const PB_DAC_1_CHANNEL: u8 = 0;
155pub const PB_DAC_2_CHANNEL: u8 = 2;
156pub const PB_MAX5825_ADDRESS: u16 = 0x1F;
157
158// LTB Power
159pub const PB_MAX7320_CHANNEL: u8 = 7;
160pub const PB_MAX7320_ADDRESS: u16 = 0x59;
161
162// I2C Options for Local Trigger Board
163// Trenz Board
164pub const LTB_TRENZ_ADDRESS: u16 = 0x3C;
165pub const LTB_TRENZ_TEMP_OFFSET: u16 = 0x00;
166// LTB Temperature Sensor (TMP112)
167pub const LTB_TMP112_ADDRESS: u16 = 0x49;
168// LTB DAC (MAX5815)
169pub const LTB_DAC_REF_VOLTAGE: f32 = 2.5;
170pub const LTB_MAX5815_ADDRESS: u16 = 0x1A;
171pub const LTB_DAC_THRESHOLD_0: f32 = 40.0; // 40.0mV
172                                           // pub const LTB_DAC_THRESHOLD_0: f32 = 50.0; // 50.0mV
173pub const LTB_DAC_THRESHOLD_1: f32 = 32.0; // 32.0mV
174                                           // pub const LTB_DAC_THRESHOLD_1: f32 = 50.0; // 50.0mV
175pub const LTB_DAC_THRESHOLD_2: f32 = 375.0; // 375.0mV
176                                            // pub const LTB_DAC_THRESHOLD_2: f32 = 150.0; // 150.0mV
177
178// I2C Options for Preamp Board
179pub const PA_TEMP_1_CHNANNEL: u8 = 7; // ADC 1, MAX11615
180pub const PA_TEMP_2_CHNANNEL: u8 = 6; // ADC 1, MAX11615
181pub const PA_TEMP_3_CHNANNEL: u8 = 5; // ADC 1, MAX11615
182pub const PA_TEMP_4_CHNANNEL: u8 = 4; // ADC 1, MAX11615
183pub const PA_TEMP_5_CHNANNEL: u8 = 4; // ADC 1, MAX11617
184pub const PA_TEMP_6_CHNANNEL: u8 = 5; // ADC 1, MAX11617
185pub const PA_TEMP_7_CHNANNEL: u8 = 6; // ADC 1, MAX11617
186pub const PA_TEMP_8_CHNANNEL: u8 = 7; // ADC 1, MAX11617
187pub const PA_TEMP_9_CHNANNEL: u8 = 7; // ADC 2, MAX11615
188pub const PA_TEMP_10_CHNANNEL: u8 = 6; // ADC 2, MAX11615
189pub const PA_TEMP_11_CHNANNEL: u8 = 5; // ADC 2, MAX11615
190pub const PA_TEMP_12_CHNANNEL: u8 = 4; // ADC 3, MAX11615
191pub const PA_TEMP_13_CHNANNEL: u8 = 4; // ADC 2, MAX11617
192pub const PA_TEMP_14_CHNANNEL: u8 = 5; // ADC 2, MAX11617
193pub const PA_TEMP_15_CHNANNEL: u8 = 6; // ADC 2, MAX11617
194pub const PA_TEMP_16_CHNANNEL: u8 = 7; // ADC 2, MAX11617
195
196pub const PA_SEN_1_CHANNEL: u8 = 3; // ADC 1, MAX11615
197pub const PA_SEN_2_CHANNEL: u8 = 2; // ADC 1, MAX11615
198pub const PA_SEN_3_CHANNEL: u8 = 1; // ADC 1, MAX11615
199pub const PA_SEN_4_CHANNEL: u8 = 0; // ADC 1, MAX11615
200pub const PA_SEN_5_CHANNEL: u8 = 10; // ADC 1, MAX11617
201pub const PA_SEN_6_CHANNEL: u8 = 9; // ADC 1, MAX11617
202pub const PA_SEN_7_CHANNEL: u8 = 8; // ADC 1, MAX11617
203pub const PA_SEN_8_CHANNEL: u8 = 0; // ADC 1, MAX11617
204pub const PA_SEN_9_CHANNEL: u8 = 3; // ADC 2, MAX11615
205pub const PA_SEN_10_CHANNEL: u8 = 2; // ADC 2, MAX11615
206pub const PA_SEN_11_CHANNEL: u8 = 1; // ADC 2, MAX11615
207pub const PA_SEN_12_CHANNEL: u8 = 0; // ADC 2, MAX11615
208pub const PA_SEN_13_CHANNEL: u8 = 10; // ADC 2, MAX11617
209pub const PA_SEN_14_CHANNEL: u8 = 9; // ADC 2, MAX11617
210pub const PA_SEN_15_CHANNEL: u8 = 8; // ADC 2, MAX11617
211pub const PA_SEN_16_CHANNEL: u8 = 0; // ADC 2, MAX11617
212
213pub const PA_DAC_1_CHANNEL: u8 = 0; // DAC1, MAX5825
214pub const PA_DAC_2_CHANNEL: u8 = 1; // DAC1, MAX5825
215pub const PA_DAC_3_CHANNEL: u8 = 2; // DAC1, MAX5825
216pub const PA_DAC_4_CHANNEL: u8 = 3; // DAC1, MAX5825
217pub const PA_DAC_5_CHANNEL: u8 = 4; // DAC1, MAX5825
218pub const PA_DAC_6_CHANNEL: u8 = 5; // DAC1, MAX5825
219pub const PA_DAC_7_CHANNEL: u8 = 6; // DAC1, MAX5825
220pub const PA_DAC_8_CHANNEL: u8 = 7; // DAC1, MAX5825
221pub const PA_DAC_9_CHANNEL: u8 = 0; // DAC2, MAX5825
222pub const PA_DAC_10_CHANNEL: u8 = 1; // DAC2, MAX5825
223pub const PA_DAC_11_CHANNEL: u8 = 2; // DAC2, MAX5825
224pub const PA_DAC_12_CHANNEL: u8 = 3; // DAC2, MAX5825
225pub const PA_DAC_13_CHANNEL: u8 = 4; // DAC2, MAX5825
226pub const PA_DAC_14_CHANNEL: u8 = 5; // DAC2, MAX5825
227pub const PA_DAC_15_CHANNEL: u8 = 6; // DAC2, MAX5825
228pub const PA_DAC_16_CHANNEL: u8 = 7; // DAC2, MAX5825
229
230pub const PA_DEFAULT_BIAS: f32 = 58.0;
231
232// I2C Options for CPC
233pub const CPC_I2C_BUS: u8 = 2;
234
235pub const CPC_TMP1075_ADDRESS: u16 = 0x48;
236
237pub const CPC_INA219_ADDRESS: u16 = 0x46;
238pub const CPC_INA219_RSHUNT: f32 = 0.03;
239pub const CPC_INA219_MEC: f32 = 1.25;
240
241pub const CPC_MAX7320_ADDRESS: u16 = 0x59;
242
243// I2C Options for TCPC
244pub const TCPC_TMP1075_ADDRESS: u16 = 0x48;
245
246pub const TCPC_INA219_ADDRESS: u16 = 0x46;
247pub const TCPC_INA219_RSHUNT: f32 = 0.03;
248pub const TCPC_INA219_MEC: f32 = 1.25;
249
250pub const TCPC_MAX7320_ADDRESS: u16 = 0x59;
251
252// Switch Constants
253pub const SWITCH1_ADDRESS: &str = "10.0.1.11:161";
254pub const SWITCH2_ADDRESS: &str = "10.0.1.12:161";
255pub const SWITCH3_ADDRESS: &str = "10.0.1.13:161";
256pub const SWITCH4_ADDRESS: &str = "10.0.1.14:161";
tof_control/constant.rs

tof_control/
constant.rs
