liftof_rb/
control.rs

1//! Convenience functions to read/write
2//!  the various control registers
3//!
4//!  
5//!  For the mapping of registers/addresses, 
6//!  see `registers.rs`
7//!
8
9use crate::registers::*;
10use crate::memory::*;
11
12use std::time::Duration;
13use std::thread;
14
15extern crate liftof_lib;
16
17/// Read the link ID from the MTB 
18///
19/// THe link ID comes from the MTB
20pub fn get_mtb_link_id() -> Result<u32, RegisterError> {
21  let mut val = read_control_reg(MT_LINK_ID)?;
22  debug!("MT_LINK_ID register {:x} reads {}!", MT_LINK_ID, val);
23  val = val & 0x01F8;
24  val = val >> 3;
25  debug!("mtb link id reads {}", val);
26  Ok(val) 
27}
28
29
30/// write header only packets when the drs is busy
31pub fn enable_evt_fragments() -> Result<(), RegisterError> {
32  trace!("Enable event fragment writing!");
33  write_control_reg(WRITE_EVENTFRAGMENT, 1)?;
34  Ok(())
35}
36
37/// use the random self trigger
38pub fn set_self_trig_rate(rate : u32) -> Result<(), RegisterError> {
39  warn!("Setting self trigger rate, writing register {}", TRIG_GEN_RATE);
40  write_control_reg(TRIG_GEN_RATE, rate)?;
41  Ok(())
42}
43
44/// do not write header only packets when the drs is busyu
45pub fn disable_evt_fragments() -> Result<(), RegisterError> {
46  trace!("Disable event fragment writing!");
47  write_control_reg(WRITE_EVENTFRAGMENT, 0)?;
48  Ok(())
49}
50
51/// enable triggering
52pub fn enable_trigger() -> Result<(), RegisterError> {
53  trace!("Enable triggers!");
54  write_control_reg(TRIGGER_ENABLE, 1)?;
55  Ok(())
56}
57
58/// stop all triggers
59pub fn disable_trigger() -> Result<(), RegisterError> {
60  trace!("Enable triggers!");
61  write_control_reg(TRIGGER_ENABLE, 0)?;
62  Ok(())
63}
64
65pub fn daq_is_busy() -> Result<bool, RegisterError> {
66  let busy = (read_control_reg(DAQ_BUSY)? & 0x2) > 0;
67  Ok(busy)
68}
69
70/// Reset the board and prepare for a new run
71///
72/// Procedure as discussed in 12/2023
73/// Trigger disable (0 to 0x11C\[0\])
74/// Set desired trigger mode  (1 to 0x114\[0\] for MTB trigger or 0 to 0x114\[0\] for software trigger)
75/// Soft reset (1 to 0x70\[0\])
76/// Check for soft reset done (read 0x74\[15\])
77/// Trigger enable (1 to 0x11C\[0\])
78pub fn soft_reset_board() -> Result<(), RegisterError> {
79  trace!("Initialize soft reset procedure!");
80  let eight_cycles = Duration::from_micros(4);
81  write_control_reg(SOFT_RESET, 0x1)?;
82  thread::sleep(eight_cycles);
83  let mut ncycles = 0;
84  while !soft_reset_done()? {
85    thread::sleep(eight_cycles);
86    ncycles += 1;
87    if ncycles % 10 == 0 {
88      error!("Not getting SOFT_RESET_DONE acknowledged. Will try DMA reset");
89      match reset_dma() {
90        Err(err) => error!("Unable to reset DMA! {err}"),
91        Ok(_)    => ()
92      }
93    }
94    if ncycles == 29 {
95      return Err(RegisterError::RegisterTimeOut);     
96    }
97  }
98  Ok(())
99}
100
101/// Check if the soft reset procedure has finished
102pub fn soft_reset_done() -> Result<bool, RegisterError> {
103  let mask : u32 = 1 << 15;
104  let value = read_control_reg(SOFT_RESET_DONE)?;
105  return Ok((value & mask) > 0)
106}
107
108
109/// Start DRS4 data acquistion
110pub fn start_drs4_daq() -> Result<(), RegisterError> {
111  trace!("SET DRS4 START");
112  write_control_reg(DRS_START, 1)?;
113  Ok(())
114}
115
116
117/// Put the daq in idle state, that is stop data taking
118pub fn idle_drs4_daq() -> Result<(), RegisterError> {
119  trace!("SET DRS4 IDLE");
120  write_control_reg(DRS_REINIT, 1)?;
121  Ok(())
122}
123
124/// Get the blob buffer occupancy for one of the two buffers
125///  
126/// This is a bit tricky. This will continuously change, as 
127/// the DRS4 is writing into the memory. At some point, it 
128/// will be full, not changing it's value anymore. At that 
129/// point, if set, the firmware has switched automatically 
130/// to the other buffer. 
131///
132/// Also, it will only read something like zero if the 
133/// DMA has completly been reset (calling dma_reset).
134/// 
135/// # Arguments
136///
137/// * which : select the blob buffer to query
138///
139///
140pub fn get_blob_buffer_occ(which : &RamBuffer) -> Result<u32, RegisterError> {
141  let address = match which {
142    RamBuffer::A => RAM_A_OCCUPANCY,
143    RamBuffer::B => RAM_B_OCCUPANCY,
144  };
145
146  let value = read_control_reg(address)?;
147  Ok(value)
148}
149
150
151/// Check if teh TRIGGER_ENABLE register is set
152pub fn get_triggers_enabled() -> Result<bool, RegisterError> {
153  let value = read_control_reg(TRIGGER_ENABLE)?;
154  Ok(value > 0)
155}
156
157/// FIXME
158pub fn get_dma_pointer() -> Result<u32, RegisterError> {
159  let value = read_control_reg(DMA_POINTER)?;
160  Ok(value)
161}
162
163/// Reset the DMA memory (blob data) and write 0s
164pub fn clear_dma_memory() -> Result<(), RegisterError> {
165  trace!("SET DMA CLEAR");
166  write_control_reg(DMA_CLEAR, 1)?;  
167  // the reset takes 8 clock cycles at 33 MHz (about 3.4 micro)
168  let eight_cycles = Duration::from_micros(4);
169  thread::sleep(eight_cycles);
170  Ok(())
171}
172
173
174/// Reset means, the memory can be used again, but it does not mean it 
175/// clears the memory.
176///
177/// The writing into the memory thus can start anywhere in memory (does 
178/// not have to be from 0)
179pub fn reset_ram_buffer_occ(which : &RamBuffer) -> Result<(), RegisterError> {
180  match which { 
181    RamBuffer::A => write_control_reg(RAM_A_OCC_RST, 0x1)?,
182    RamBuffer::B => write_control_reg(RAM_B_OCC_RST, 0x1)?
183  };
184  // the reset takes 8 clock cycles at 33 MHz (about 3.4 micro)
185  let eight_cycles = Duration::from_micros(4);
186  thread::sleep(eight_cycles);
187  Ok(())
188}
189
190/// Get the recorded triggers by the DRS4
191pub fn get_trigger_rate() -> Result<u32, RegisterError> {
192  let value = read_control_reg(TRIGGER_RATE)?;
193  Ok(value)
194}
195
196/// Get the rate of the lost triggers by the DRS4
197pub fn get_lost_trigger_rate() -> Result<u32, RegisterError> {
198  let value = read_control_reg(LOST_TRIGGER_RATE)?;
199  Ok(value)
200}
201
202/// Get the event counter from the DRS4
203///
204/// The event counter is NOT the event id comming from 
205/// the master trigger. It is simply the number of 
206/// events observed since the last reset.
207///
208pub fn get_event_count() -> Result<u32, RegisterError> {
209  let value = read_control_reg(CNT_EVENT)?;
210  Ok(value)
211}
212
213/// Get the event counter as sent from the MTB
214pub fn get_event_count_mt() -> Result<u32, RegisterError> {
215  let value = read_control_reg(MT_EVENT_CNT)?;
216  Ok(value)
217}
218
219/// Get the rate as sent from the MTB
220pub fn get_event_rate_mt() -> Result<u32, RegisterError> {
221  let value = read_control_reg(MT_TRIG_RATE)?;
222  Ok(value)
223}
224
225/// Get the lost events event counter from the DRS4
226pub fn get_lost_event_count() -> Result<u32, RegisterError> {
227  let value = read_control_reg(CNT_LOST_EVENT)?;
228  Ok(value)
229}
230
231/// This simply sets the configure bit.
232///
233/// Unclear what it actually does.
234/// FIXME
235pub fn set_drs4_configure() -> Result<(), RegisterError> {
236  trace!("SET DRS4 CONFIGURE");
237  write_control_reg(DRS_CONFIGURE, 1)?;
238  Ok(())
239}
240
241/// Force a trigger
242///
243/// _If I understand it correctly, this is a single trigger_
244///
245pub fn trigger() -> Result<(), RegisterError> {
246  //warn!("Setting force trigger mode!");
247  write_control_reg(FORCE_TRIG, 1)?;
248  Ok(())
249}
250
251/// Reset of the internal event counter
252///
253///  This is NOT the event id.
254pub fn reset_drs_event_ctr() -> Result<(), RegisterError> {
255  trace!("SET DRS4 EV CNT RESET");
256  write_control_reg(CNT_RESET, 1)?;
257  Ok(())
258}
259
260pub fn reset_daq() -> Result<(), RegisterError> {
261  trace!("SET DAQ RESET");
262  write_control_reg(DAQ_RESET, 1)?;
263  Ok(())
264}
265
266pub fn reset_drs() -> Result<(), RegisterError> {
267  trace!("SET DRS RESET");
268  write_control_reg(DRS_REINIT, 1)?;
269  Ok(())
270}
271
272///! Resets the DMA state machine.
273pub fn reset_dma() -> Result<(), RegisterError> {
274  trace!("SET DMA RESET");
275  write_control_reg(DMA_RESET, 1)?;
276  // the reset takes 8 clock cycles at 33 MHz (about 3.4 micro)
277  let eight_cycles = Duration::from_micros(4);
278  thread::sleep(eight_cycles);
279  Ok(())
280}
281
282
283///! Toggle between the data buffers A and B
284pub fn switch_ram_buffer() -> Result<(), RegisterError> {
285  trace!("SET DMA DATA BUFF TOGGLE");
286  write_control_reg(TOGGLE_RAM, 1)?;
287  Ok(())
288}
289
290///! The device DNA is a unique identifier
291pub fn get_device_dna() -> Result<u64, RegisterError> {
292  let lsb = read_control_reg(DNA_LSBS)?;
293  let msb = read_control_reg(DNA_MSBS)?;
294  let mut value : u64 = 0;
295  value = value | (msb as u64) << 32;
296  value = value | lsb as u64;
297  Ok(value)
298}
299
300
301/// Enable the readout of all channels + the 9th channel
302pub fn set_readout_all_channels_and_ch9() -> Result<(), RegisterError> {
303  warn!("This might be buggy!");
304  let all_channels : u32 = 511;
305  let ch_9         : u32 = 512;
306  let value = all_channels | ch_9;
307  trace!("SET DRS4 READOUT MASK");
308  write_control_reg(READOUT_MASK, value)?;
309  Ok(())
310}
311
312/// Enable active channels by not touching the ch9 bits
313pub fn set_active_channel_mask(ch_mask : u8) -> Result<(), RegisterError> {
314  let mut value   = read_control_reg(READOUT_MASK)?;
315  // FIXME - do debug! instead.
316  println!("==> Got current channel mask! {value}");
317  let ch9_part     = value & 0xFF00; // set all ch to 0;
318  value            = ch9_part | ch_mask as u32;
319  write_control_reg(READOUT_MASK, value)?;
320  println!("==> Wrote {value} to channel mask register!");
321  Ok(())
322}
323
324pub fn set_active_channel_mask_with_ch9(ch_mask : u32) -> Result<(), RegisterError> {
325  let ch_9  : u32 = 256;
326  let value = ch_mask | ch_9;
327  write_control_reg(READOUT_MASK, value)?;
328  Ok(())
329}
330
331/// Enable the master trigger mode
332pub fn set_master_trigger_mode() -> Result<(), RegisterError> {
333  trace!("SET DRS4 MT MODE");
334  write_control_reg(MT_TRIGGER_MODE, 1)?;
335  Ok(())
336}
337
338/// Disable the master trigger
339pub fn disable_master_trigger_mode() -> Result<(), RegisterError> {
340  warn!("Disabeling master trigger mode");
341  write_control_reg(MT_TRIGGER_MODE, 0)?;
342  Ok(())
343}
344
345
346///! Get the board ID from the control registers.
347pub fn get_board_id() -> Result<u32, RegisterError> { 
348  let board_id = read_control_reg(BOARD_ID)?;
349  Ok(board_id)
350}
351
352///! Get the board ID from the control registers.
353pub fn get_board_id_string() -> Result<String, RegisterError> { 
354  let board_id = get_board_id()?;
355  let board_id_string = liftof_lib::to_board_id_string(board_id);
356  Ok(board_id_string)
357}
358
359/// Read te last DRS4 Deadtime
360pub fn get_deadtime() -> Result<u32, RegisterError> {
361  let deadtime = read_control_reg(DRS_DEADTIME)?;
362  Ok(deadtime & 0xffff)
363}
liftof_rb/control.rs

liftof_rb/
control.rs
