liftof_rb/
control.rs

1//! Convenience functions to read/write
2//!  the various control registers
3//!
4//!  
5//!  For the mapping of registers/addresses, 
6//!  see `registers.rs`
7//!
8
9use crate::registers::*;
10use crate::memory::*;
11
12use std::time::Duration;
13use std::thread;
14
15//use gondola_core::prelude::*;
16use gondola_core::tof::to_board_id_string;
17
18/// Read the link ID from the MTB 
19///
20/// THe link ID comes from the MTB
21pub fn get_mtb_link_id() -> Result<u32, RegisterError> {
22  let mut val = read_control_reg(MT_LINK_ID)?;
23  debug!("MT_LINK_ID register {:x} reads {}!", MT_LINK_ID, val);
24  val = val & 0x01F8;
25  val = val >> 3;
26  debug!("mtb link id reads {}", val);
27  Ok(val) 
28}
29
30
31/// write header only packets when the drs is busy
32pub fn enable_evt_fragments() -> Result<(), RegisterError> {
33  trace!("Enable event fragment writing!");
34  write_control_reg(WRITE_EVENTFRAGMENT, 1)?;
35  Ok(())
36}
37
38/// use the random self trigger
39pub fn set_self_trig_rate(rate : u32) -> Result<(), RegisterError> {
40  warn!("Setting self trigger rate, writing register {}", TRIG_GEN_RATE);
41  write_control_reg(TRIG_GEN_RATE, rate)?;
42  Ok(())
43}
44
45/// do not write header only packets when the drs is busyu
46pub fn disable_evt_fragments() -> Result<(), RegisterError> {
47  trace!("Disable event fragment writing!");
48  write_control_reg(WRITE_EVENTFRAGMENT, 0)?;
49  Ok(())
50}
51
52/// enable triggering
53pub fn enable_trigger() -> Result<(), RegisterError> {
54  trace!("Enable triggers!");
55  write_control_reg(TRIGGER_ENABLE, 1)?;
56  Ok(())
57}
58
59/// stop all triggers
60pub fn disable_trigger() -> Result<(), RegisterError> {
61  trace!("Enable triggers!");
62  write_control_reg(TRIGGER_ENABLE, 0)?;
63  Ok(())
64}
65
66pub fn daq_is_busy() -> Result<bool, RegisterError> {
67  let busy = (read_control_reg(DAQ_BUSY)? & 0x2) > 0;
68  Ok(busy)
69}
70
71/// Reset the board and prepare for a new run
72///
73/// Procedure as discussed in 12/2023
74/// Trigger disable (0 to 0x11C\[0\])
75/// Set desired trigger mode  (1 to 0x114\[0\] for MTB trigger or 0 to 0x114\[0\] for software trigger)
76/// Soft reset (1 to 0x70\[0\])
77/// Check for soft reset done (read 0x74\[15\])
78/// Trigger enable (1 to 0x11C\[0\])
79pub fn soft_reset_board() -> Result<(), RegisterError> {
80  trace!("Initialize soft reset procedure!");
81  let eight_cycles = Duration::from_micros(4);
82  write_control_reg(SOFT_RESET, 0x1)?;
83  thread::sleep(eight_cycles);
84  let mut ncycles = 0;
85  while !soft_reset_done()? {
86    thread::sleep(eight_cycles);
87    ncycles += 1;
88    if ncycles % 10 == 0 {
89      error!("Not getting SOFT_RESET_DONE acknowledged. Will try DMA reset");
90      match reset_dma() {
91        Err(err) => error!("Unable to reset DMA! {err}"),
92        Ok(_)    => ()
93      }
94    }
95    if ncycles == 29 {
96      return Err(RegisterError::RegisterTimeOut);     
97    }
98  }
99  Ok(())
100}
101
102/// Check if the soft reset procedure has finished
103pub fn soft_reset_done() -> Result<bool, RegisterError> {
104  let mask : u32 = 1 << 15;
105  let value = read_control_reg(SOFT_RESET_DONE)?;
106  return Ok((value & mask) > 0)
107}
108
109
110/// Start DRS4 data acquistion
111pub fn start_drs4_daq() -> Result<(), RegisterError> {
112  trace!("SET DRS4 START");
113  write_control_reg(DRS_START, 1)?;
114  Ok(())
115}
116
117
118/// Put the daq in idle state, that is stop data taking
119pub fn idle_drs4_daq() -> Result<(), RegisterError> {
120  trace!("SET DRS4 IDLE");
121  write_control_reg(DRS_REINIT, 1)?;
122  Ok(())
123}
124
125/// Get the blob buffer occupancy for one of the two buffers
126///  
127/// This is a bit tricky. This will continuously change, as 
128/// the DRS4 is writing into the memory. At some point, it 
129/// will be full, not changing it's value anymore. At that 
130/// point, if set, the firmware has switched automatically 
131/// to the other buffer. 
132///
133/// Also, it will only read something like zero if the 
134/// DMA has completly been reset (calling dma_reset).
135/// 
136/// # Arguments
137///
138/// * which : select the blob buffer to query
139///
140///
141pub fn get_blob_buffer_occ(which : &RamBuffer) -> Result<u32, RegisterError> {
142  let address = match which {
143    RamBuffer::A => RAM_A_OCCUPANCY,
144    RamBuffer::B => RAM_B_OCCUPANCY,
145  };
146
147  let value = read_control_reg(address)?;
148  Ok(value)
149}
150
151
152/// Check if teh TRIGGER_ENABLE register is set
153pub fn get_triggers_enabled() -> Result<bool, RegisterError> {
154  let value = read_control_reg(TRIGGER_ENABLE)?;
155  Ok(value > 0)
156}
157
158/// FIXME
159pub fn get_dma_pointer() -> Result<u32, RegisterError> {
160  let value = read_control_reg(DMA_POINTER)?;
161  Ok(value)
162}
163
164/// Reset the DMA memory (blob data) and write 0s
165pub fn clear_dma_memory() -> Result<(), RegisterError> {
166  trace!("SET DMA CLEAR");
167  write_control_reg(DMA_CLEAR, 1)?;  
168  // the reset takes 8 clock cycles at 33 MHz (about 3.4 micro)
169  let eight_cycles = Duration::from_micros(4);
170  thread::sleep(eight_cycles);
171  Ok(())
172}
173
174
175/// Reset means, the memory can be used again, but it does not mean it 
176/// clears the memory.
177///
178/// The writing into the memory thus can start anywhere in memory (does 
179/// not have to be from 0)
180pub fn reset_ram_buffer_occ(which : &RamBuffer) -> Result<(), RegisterError> {
181  match which { 
182    RamBuffer::A => write_control_reg(RAM_A_OCC_RST, 0x1)?,
183    RamBuffer::B => write_control_reg(RAM_B_OCC_RST, 0x1)?
184  };
185  // the reset takes 8 clock cycles at 33 MHz (about 3.4 micro)
186  let eight_cycles = Duration::from_micros(4);
187  thread::sleep(eight_cycles);
188  Ok(())
189}
190
191/// Get the recorded triggers by the DRS4
192pub fn get_trigger_rate() -> Result<u32, RegisterError> {
193  let value = read_control_reg(TRIGGER_RATE)?;
194  Ok(value)
195}
196
197/// Get the rate of the lost triggers by the DRS4
198pub fn get_lost_trigger_rate() -> Result<u32, RegisterError> {
199  let value = read_control_reg(LOST_TRIGGER_RATE)?;
200  Ok(value)
201}
202
203/// Get the event counter from the DRS4
204///
205/// The event counter is NOT the event id comming from 
206/// the master trigger. It is simply the number of 
207/// events observed since the last reset.
208///
209pub fn get_event_count() -> Result<u32, RegisterError> {
210  let value = read_control_reg(CNT_EVENT)?;
211  Ok(value)
212}
213
214/// Get the event counter as sent from the MTB
215pub fn get_event_count_mt() -> Result<u32, RegisterError> {
216  let value = read_control_reg(MT_EVENT_CNT)?;
217  Ok(value)
218}
219
220/// Get the rate as sent from the MTB
221pub fn get_event_rate_mt() -> Result<u32, RegisterError> {
222  let value = read_control_reg(MT_TRIG_RATE)?;
223  Ok(value)
224}
225
226/// Get the lost events event counter from the DRS4
227pub fn get_lost_event_count() -> Result<u32, RegisterError> {
228  let value = read_control_reg(CNT_LOST_EVENT)?;
229  Ok(value)
230}
231
232/// This simply sets the configure bit.
233///
234/// Unclear what it actually does.
235/// FIXME
236pub fn set_drs4_configure() -> Result<(), RegisterError> {
237  trace!("SET DRS4 CONFIGURE");
238  write_control_reg(DRS_CONFIGURE, 1)?;
239  Ok(())
240}
241
242/// Force a trigger
243///
244/// _If I understand it correctly, this is a single trigger_
245///
246pub fn trigger() -> Result<(), RegisterError> {
247  //warn!("Setting force trigger mode!");
248  write_control_reg(FORCE_TRIG, 1)?;
249  Ok(())
250}
251
252/// Reset of the internal event counter
253///
254///  This is NOT the event id.
255pub fn reset_drs_event_ctr() -> Result<(), RegisterError> {
256  trace!("SET DRS4 EV CNT RESET");
257  write_control_reg(CNT_RESET, 1)?;
258  Ok(())
259}
260
261pub fn reset_daq() -> Result<(), RegisterError> {
262  trace!("SET DAQ RESET");
263  write_control_reg(DAQ_RESET, 1)?;
264  Ok(())
265}
266
267pub fn reset_drs() -> Result<(), RegisterError> {
268  trace!("SET DRS RESET");
269  write_control_reg(DRS_REINIT, 1)?;
270  Ok(())
271}
272
273///! Resets the DMA state machine.
274pub fn reset_dma() -> Result<(), RegisterError> {
275  trace!("SET DMA RESET");
276  write_control_reg(DMA_RESET, 1)?;
277  // the reset takes 8 clock cycles at 33 MHz (about 3.4 micro)
278  let eight_cycles = Duration::from_micros(4);
279  thread::sleep(eight_cycles);
280  Ok(())
281}
282
283
284///! Toggle between the data buffers A and B
285pub fn switch_ram_buffer() -> Result<(), RegisterError> {
286  trace!("SET DMA DATA BUFF TOGGLE");
287  write_control_reg(TOGGLE_RAM, 1)?;
288  Ok(())
289}
290
291///! The device DNA is a unique identifier
292pub fn get_device_dna() -> Result<u64, RegisterError> {
293  let lsb = read_control_reg(DNA_LSBS)?;
294  let msb = read_control_reg(DNA_MSBS)?;
295  let mut value : u64 = 0;
296  value = value | (msb as u64) << 32;
297  value = value | lsb as u64;
298  Ok(value)
299}
300
301
302/// Enable the readout of all channels + the 9th channel
303pub fn set_readout_all_channels_and_ch9() -> Result<(), RegisterError> {
304  warn!("This might be buggy!");
305  let all_channels : u32 = 511;
306  let ch_9         : u32 = 512;
307  let value = all_channels | ch_9;
308  trace!("SET DRS4 READOUT MASK");
309  write_control_reg(READOUT_MASK, value)?;
310  Ok(())
311}
312
313/// Enable active channels by not touching the ch9 bits
314pub fn set_active_channel_mask(ch_mask : u8) -> Result<(), RegisterError> {
315  let mut value   = read_control_reg(READOUT_MASK)?;
316  // FIXME - do debug! instead.
317  println!("==> Got current channel mask! {value}");
318  let ch9_part     = value & 0xFF00; // set all ch to 0;
319  value            = ch9_part | ch_mask as u32;
320  write_control_reg(READOUT_MASK, value)?;
321  println!("==> Wrote {value} to channel mask register!");
322  Ok(())
323}
324
325pub fn set_active_channel_mask_with_ch9(ch_mask : u32) -> Result<(), RegisterError> {
326  let ch_9  : u32 = 256;
327  let value = ch_mask | ch_9;
328  write_control_reg(READOUT_MASK, value)?;
329  Ok(())
330}
331
332/// Enable the master trigger mode
333pub fn set_master_trigger_mode() -> Result<(), RegisterError> {
334  trace!("SET DRS4 MT MODE");
335  write_control_reg(MT_TRIGGER_MODE, 1)?;
336  Ok(())
337}
338
339/// Disable the master trigger
340pub fn disable_master_trigger_mode() -> Result<(), RegisterError> {
341  warn!("Disabeling master trigger mode");
342  write_control_reg(MT_TRIGGER_MODE, 0)?;
343  Ok(())
344}
345
346
347///! Get the board ID from the control registers.
348pub fn get_board_id() -> Result<u32, RegisterError> { 
349  let board_id = read_control_reg(BOARD_ID)?;
350  Ok(board_id)
351}
352
353///! Get the board ID from the control registers.
354pub fn get_board_id_string() -> Result<String, RegisterError> { 
355  let board_id = get_board_id()?;
356  let board_id_string = to_board_id_string(board_id);
357  Ok(board_id_string)
358}
359
360/// Read te last DRS4 Deadtime
361pub fn get_deadtime() -> Result<u32, RegisterError> {
362  let deadtime = read_control_reg(DRS_DEADTIME)?;
363  Ok(deadtime & 0xffff)
364}