1use crate::registers::*;
10use crate::memory::*;
11
12use std::time::Duration;
13use std::thread;
14
15use gondola_core::tof::to_board_id_string;
17
18pub fn get_mtb_link_id() -> Result<u32, RegisterError> {
22 let mut val = read_control_reg(MT_LINK_ID)?;
23 debug!("MT_LINK_ID register {:x} reads {}!", MT_LINK_ID, val);
24 val = val & 0x01F8;
25 val = val >> 3;
26 debug!("mtb link id reads {}", val);
27 Ok(val)
28}
29
30
31pub fn enable_evt_fragments() -> Result<(), RegisterError> {
33 trace!("Enable event fragment writing!");
34 write_control_reg(WRITE_EVENTFRAGMENT, 1)?;
35 Ok(())
36}
37
38pub fn set_self_trig_rate(rate : u32) -> Result<(), RegisterError> {
40 warn!("Setting self trigger rate, writing register {}", TRIG_GEN_RATE);
41 write_control_reg(TRIG_GEN_RATE, rate)?;
42 Ok(())
43}
44
45pub fn disable_evt_fragments() -> Result<(), RegisterError> {
47 trace!("Disable event fragment writing!");
48 write_control_reg(WRITE_EVENTFRAGMENT, 0)?;
49 Ok(())
50}
51
52pub fn enable_trigger() -> Result<(), RegisterError> {
54 trace!("Enable triggers!");
55 write_control_reg(TRIGGER_ENABLE, 1)?;
56 Ok(())
57}
58
59pub fn disable_trigger() -> Result<(), RegisterError> {
61 trace!("Enable triggers!");
62 write_control_reg(TRIGGER_ENABLE, 0)?;
63 Ok(())
64}
65
66pub fn daq_is_busy() -> Result<bool, RegisterError> {
67 let busy = (read_control_reg(DAQ_BUSY)? & 0x2) > 0;
68 Ok(busy)
69}
70
71pub fn soft_reset_board() -> Result<(), RegisterError> {
80 trace!("Initialize soft reset procedure!");
81 let eight_cycles = Duration::from_micros(4);
82 write_control_reg(SOFT_RESET, 0x1)?;
83 thread::sleep(eight_cycles);
84 let mut ncycles = 0;
85 while !soft_reset_done()? {
86 thread::sleep(eight_cycles);
87 ncycles += 1;
88 if ncycles % 10 == 0 {
89 error!("Not getting SOFT_RESET_DONE acknowledged. Will try DMA reset");
90 match reset_dma() {
91 Err(err) => error!("Unable to reset DMA! {err}"),
92 Ok(_) => ()
93 }
94 }
95 if ncycles == 29 {
96 return Err(RegisterError::RegisterTimeOut);
97 }
98 }
99 Ok(())
100}
101
102pub fn soft_reset_done() -> Result<bool, RegisterError> {
104 let mask : u32 = 1 << 15;
105 let value = read_control_reg(SOFT_RESET_DONE)?;
106 return Ok((value & mask) > 0)
107}
108
109
110pub fn start_drs4_daq() -> Result<(), RegisterError> {
112 trace!("SET DRS4 START");
113 write_control_reg(DRS_START, 1)?;
114 Ok(())
115}
116
117
118pub fn idle_drs4_daq() -> Result<(), RegisterError> {
120 trace!("SET DRS4 IDLE");
121 write_control_reg(DRS_REINIT, 1)?;
122 Ok(())
123}
124
125pub fn get_blob_buffer_occ(which : &RamBuffer) -> Result<u32, RegisterError> {
142 let address = match which {
143 RamBuffer::A => RAM_A_OCCUPANCY,
144 RamBuffer::B => RAM_B_OCCUPANCY,
145 };
146
147 let value = read_control_reg(address)?;
148 Ok(value)
149}
150
151
152pub fn get_triggers_enabled() -> Result<bool, RegisterError> {
154 let value = read_control_reg(TRIGGER_ENABLE)?;
155 Ok(value > 0)
156}
157
158pub fn get_dma_pointer() -> Result<u32, RegisterError> {
160 let value = read_control_reg(DMA_POINTER)?;
161 Ok(value)
162}
163
164pub fn clear_dma_memory() -> Result<(), RegisterError> {
166 trace!("SET DMA CLEAR");
167 write_control_reg(DMA_CLEAR, 1)?;
168 let eight_cycles = Duration::from_micros(4);
170 thread::sleep(eight_cycles);
171 Ok(())
172}
173
174
175pub fn reset_ram_buffer_occ(which : &RamBuffer) -> Result<(), RegisterError> {
181 match which {
182 RamBuffer::A => write_control_reg(RAM_A_OCC_RST, 0x1)?,
183 RamBuffer::B => write_control_reg(RAM_B_OCC_RST, 0x1)?
184 };
185 let eight_cycles = Duration::from_micros(4);
187 thread::sleep(eight_cycles);
188 Ok(())
189}
190
191pub fn get_trigger_rate() -> Result<u32, RegisterError> {
193 let value = read_control_reg(TRIGGER_RATE)?;
194 Ok(value)
195}
196
197pub fn get_lost_trigger_rate() -> Result<u32, RegisterError> {
199 let value = read_control_reg(LOST_TRIGGER_RATE)?;
200 Ok(value)
201}
202
203pub fn get_event_count() -> Result<u32, RegisterError> {
210 let value = read_control_reg(CNT_EVENT)?;
211 Ok(value)
212}
213
214pub fn get_event_count_mt() -> Result<u32, RegisterError> {
216 let value = read_control_reg(MT_EVENT_CNT)?;
217 Ok(value)
218}
219
220pub fn get_event_rate_mt() -> Result<u32, RegisterError> {
222 let value = read_control_reg(MT_TRIG_RATE)?;
223 Ok(value)
224}
225
226pub fn get_lost_event_count() -> Result<u32, RegisterError> {
228 let value = read_control_reg(CNT_LOST_EVENT)?;
229 Ok(value)
230}
231
232pub fn set_drs4_configure() -> Result<(), RegisterError> {
237 trace!("SET DRS4 CONFIGURE");
238 write_control_reg(DRS_CONFIGURE, 1)?;
239 Ok(())
240}
241
242pub fn trigger() -> Result<(), RegisterError> {
247 write_control_reg(FORCE_TRIG, 1)?;
249 Ok(())
250}
251
252pub fn reset_drs_event_ctr() -> Result<(), RegisterError> {
256 trace!("SET DRS4 EV CNT RESET");
257 write_control_reg(CNT_RESET, 1)?;
258 Ok(())
259}
260
261pub fn reset_daq() -> Result<(), RegisterError> {
262 trace!("SET DAQ RESET");
263 write_control_reg(DAQ_RESET, 1)?;
264 Ok(())
265}
266
267pub fn reset_drs() -> Result<(), RegisterError> {
268 trace!("SET DRS RESET");
269 write_control_reg(DRS_REINIT, 1)?;
270 Ok(())
271}
272
273pub fn reset_dma() -> Result<(), RegisterError> {
275 trace!("SET DMA RESET");
276 write_control_reg(DMA_RESET, 1)?;
277 let eight_cycles = Duration::from_micros(4);
279 thread::sleep(eight_cycles);
280 Ok(())
281}
282
283
284pub fn switch_ram_buffer() -> Result<(), RegisterError> {
286 trace!("SET DMA DATA BUFF TOGGLE");
287 write_control_reg(TOGGLE_RAM, 1)?;
288 Ok(())
289}
290
291pub fn get_device_dna() -> Result<u64, RegisterError> {
293 let lsb = read_control_reg(DNA_LSBS)?;
294 let msb = read_control_reg(DNA_MSBS)?;
295 let mut value : u64 = 0;
296 value = value | (msb as u64) << 32;
297 value = value | lsb as u64;
298 Ok(value)
299}
300
301
302pub fn set_readout_all_channels_and_ch9() -> Result<(), RegisterError> {
304 warn!("This might be buggy!");
305 let all_channels : u32 = 511;
306 let ch_9 : u32 = 512;
307 let value = all_channels | ch_9;
308 trace!("SET DRS4 READOUT MASK");
309 write_control_reg(READOUT_MASK, value)?;
310 Ok(())
311}
312
313pub fn set_active_channel_mask(ch_mask : u8) -> Result<(), RegisterError> {
315 let mut value = read_control_reg(READOUT_MASK)?;
316 println!("==> Got current channel mask! {value}");
318 let ch9_part = value & 0xFF00; value = ch9_part | ch_mask as u32;
320 write_control_reg(READOUT_MASK, value)?;
321 println!("==> Wrote {value} to channel mask register!");
322 Ok(())
323}
324
325pub fn set_active_channel_mask_with_ch9(ch_mask : u32) -> Result<(), RegisterError> {
326 let ch_9 : u32 = 256;
327 let value = ch_mask | ch_9;
328 write_control_reg(READOUT_MASK, value)?;
329 Ok(())
330}
331
332pub fn set_master_trigger_mode() -> Result<(), RegisterError> {
334 trace!("SET DRS4 MT MODE");
335 write_control_reg(MT_TRIGGER_MODE, 1)?;
336 Ok(())
337}
338
339pub fn disable_master_trigger_mode() -> Result<(), RegisterError> {
341 warn!("Disabeling master trigger mode");
342 write_control_reg(MT_TRIGGER_MODE, 0)?;
343 Ok(())
344}
345
346
347pub fn get_board_id() -> Result<u32, RegisterError> {
349 let board_id = read_control_reg(BOARD_ID)?;
350 Ok(board_id)
351}
352
353pub fn get_board_id_string() -> Result<String, RegisterError> {
355 let board_id = get_board_id()?;
356 let board_id_string = to_board_id_string(board_id);
357 Ok(board_id_string)
358}
359
360pub fn get_deadtime() -> Result<u32, RegisterError> {
362 let deadtime = read_control_reg(DRS_DEADTIME)?;
363 Ok(deadtime & 0xffff)
364}