Module registers

Source

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MasterTriggerBoard registers

This should be the same as the reference doucmentation on the UCLA gitlab server

This currently does NOT sync itself with the reposity, so we have to take extra care that these numbers are correct!.

All registers are 32bit

Structs§

MTBRegister: A single 32bit register on the MTB with an associated mask to mask parts of ig

Constants§

ANY_TRIGGER_BLOCKED_RATE: Rate of Any trigger blocked due to prescaler or disable ANY_TRIGGER_BLOCKED_RATE 0x251 0x944 [23:0] r Rate of this trigger blocked due to prescaler or disable
ANY_TRIG_IS_GLOBAL: Add any trigger to all triggers ANY_TRIG_IS_GLOBAL 0xb 0x2c 0 rw 0x0
ANY_TRIG_PRESCALE: Any 2 paddle combination. Can be used with a prescale factor. If the prescale is 0, then it will be disabled ANY_TRIG_PRESCALE 0x40 0x100 [31:0] rw 0x0 Prescale value for the ANY trigger. 0 == 0% (off), 2**32-1 == 100%
CH_0_24: Set fire bits for LTB Ch 0-24 CH_0_24 0x101 0x404 [24:0] rw 0x0
CH_25_49: CH_25_49 0x102 0x408 [24:0] rw 0x0
CH_50_74: CH_50_74 0x103 0x40c rw [24:0] 0x0
CH_75_99: CH_75_99 0x104 0x410
CH_100_124: CH_100_124 0x105 0x414
CH_125_149: CH_125_149 0x106 0x418
CH_150_174: CH_150_174 0x107
CH_175_199: CH 175-199 0x108
CLOCK_RATE: FPGA System clock rate CLOCK_RATE 0x1 0x4 [31:0] r system clock frequency
CONFIGURABLE_TRIGGER_EN: Enable the configurable trigger (has to be enable for any fine-grained threshhold setting to come into effect) CONFIGURABLE_TRIGGER_EN 0x14 0x50 31 rw 0x0 Enable the configurable trigger
CORTINA_THRESH: Set the (nhit) threshold for the cortina panesl
CUBE_BOT_THRESH: Set the (nhit) threshold for the cube bottom panesl
CUBE_CORNER_THRESH: Set the (nhit) threshold for the cube bottom panesl
CUBE_SIDE_THRESH: Set the (nhit) threshold for the cube side panesl
CUBE_TOP_THRESH: Set the (nhit) threshold for the cube top panesl
ETH_RX_BAD_FCS_CNT: ETH_RX_BAD_FCS_CNT 0x3d 0xf4 [31:16] Ethernet MAC bad fcs
ETH_RX_BAD_FRAME_CNT: ETH_RX_BAD_FRAME_CNT 0x3d 0xf4 [15:0] Ethernet MAC bad frame error
EVENT_CNT: The global event id EVENT_CNT 0xd 0x34 [31:0] r Event Counter
EVENT_CNT_RESET: Reset the global event id (excecute with caution) EVENT_CNT_RESET 0xc 0x30 0 w Pulse Write 1 to reset the event counter
EVQ_DATA: DAQ data payload. An event will be broken down into multiple u32, which wlll be all accessible through this register. The EVQ_SIZE register tells how many times this register hast to be read (the actual value is twice this number, since internally the MTB operates on 16bit registers) DATA 0x11 0x44 [31:0] r DAQ Read Data
EVQ_EMPTY: The DAQ buffer is empty FULL 0x12 0x48 1 r DAQ Buffer Full
EVQ_FULL: The DAQ buffer is full FULL 0x12 0x48 0 r DAQ Buffer Full
EVQ_NUM_EVENTS: DAQ buffer size (in events) NUM_EVENTS 0x13 0x4c [13:0] r DAQ Buffer Number of Event
EVQ_RESET: Reset the DAQ buffer (this does NOT reset the event ID) RESET 0x10 0x40 0 w Pulse DAQ Buffer Reset
EVQ_SIZE: DAQ data queue SIZE. This stores twice the number of times the EVQ_DATA register has to be read out to obtain a complete event SIZE 0x13 0x4c [31:16] r DAQ Buffer Head Event Size
FORCE_TRIGGER: Force a trigger (has to be previously set) FORCE_TRIGGER 0x8 0x20 0 w Pulse Write 1 to generate a trigger
GAPS_TRIGGER_BLOCKED_RATE: Rate of GAPS trigger blocked due to prescaler or disable GAPS_TRIGGER_BLOCKED_RATE 0x24f 0x93c [23:0]
GAPS_TRIGGER_EN: Enable the Gaps (antiparticle) trigger GAPS_TRIGGER_EN 0x14 0x50 24 rw 0x0 Enable the gaps trigger.
GAPS_TRIG_PRESCALE: Prescale value for the GAPS trigger. 0 == 0% (off), 2**32-1 == 100% GAPS_TRIG_PRESCALE 0x248 0x920 [31:0] rw 0xffffffff
INNER_TOF_THRESH: Total inner tof (cube) threshold (nhits)
LOST_TRIGGER_RATE: Set the (nhit) threshold for the cortina panesl
LT0: LTB Hit counter for slot 0
LT0_CHMASK: LTB channel mask, set 1 to a channel to mask (deactivate it)
LT1: LTB Hit counter for slot 1
LT2: LTB Hit counter for slot 2
LT3: LTB Hit counter for slot 3
LT4: LTB Hit counter for slot 4
LT5: LTB Hit counter for slot 5
LT6: LTB Hit counter for slot 6 LT6 0x26 0x80 [23:0] r hit count on LT=6
LT7: LTB Hit counter for slot 7 LT7 0x27 0x80 [23:0] r hit count on LT=7
LT8: LTB Hit counter for slot 8 LT8 0x28 0x80 [23:0] r hit count on LT=8
LT9: LTB Hit counter for slot 9 LT8 0x29 0x80 [23:0] r hit count on LT=9
LT1_CHMASK: LT1 channel mask, set 1 to a channel to mask (deactivate it)
LT2_CHMASK: LT2 channel mask, set 1 to a channel to mask (deactivate it)
LT3_CHMASK: LT3 channel mask, set 1 to a channel to mask (deactivate it)
LT4_CHMASK: LT4 channel mask, set 1 to a channel to mask (deactivate it)
LT5_CHMASK: LT5 channel mask, set 1 to a channel to mask (deactivate it)
LT6_CHMASK: LT6 channel mask, set 1 to a channel to mask (deactivate it)
LT7_CHMASK: LT7 channel mask, set 1 to a channel to mask (deactivate it)
LT8_CHMASK: LT8 channel mask, set 1 to a channel to mask (deactivate it)
LT9_CHMASK: LT9 channel mask, set 1 to a channel to mask (deactivate it)
LT10: LTB Hit counter for slot 10 LT10 0x2a 0x80 [23:0] r hit count on LT=10
LT11: LTB Hit counter for slot 11 LT11 0x2b 0x80 [23:0] r hit count on LT=11
LT12: LTB Hit counter for slot 12 LT12 0x2c 0x80 [23:0] r hit count on LT=12
LT13: LTB Hit counter for slot 13 LT13 0x2d 0x80 [23:0] r hit count on LT=13
LT14: LTB Hit counter for slot 14 LT14 0x2e 0x80 [23:0] r hit count on LT=14
LT15: LTB Hit counter for slot 15 LT15 0x2f 0x80 [23:0] r hit count on LT=15
LT16: LTB Hit counter for slot 16 LT16 0x30 0x80 [23:0] r hit count on LT=16
LT17: LTB Hit counter for slot 17 LT17 0x31 0x80 [23:0] r hit count on LT=17
LT18: LTB Hit counter for slot 18 LT18 0x32 0x80 [23:0] r hit count on LT=18
LT19: LTB Hit counter for slot 19 LT19 0x33 0x80 [23:0] r hit count on LT=19
LT20: LTB Hit counter for slot 20 LT20 0x34 0x80 [23:0] r hit count on LT=20
LT21: LTB Hit counter for slot 0 LT21 0x35 0x80 [23:0] r hit count on LT=21
LT22: LTB Hit counter for slot 22 LT22 0x36 0x80 [23:0] r hit count on LT=22
LT23: LTB Hit counter for slot 23 LT23 0x37 0x80 [23:0] r hit count on LT=23
LT24: LTB Hit counter for slot 24 LT24 0x38 0x80 [23:0] r hit count on LT=38
LT10_CHMASK: LT10 channel mask, set 1 to a channel to mask (deactivate it)
LT11_CHMASK: LT11 channel mask, set 1 to a channel to mask (deactivate it)
LT12_CHMASK: LT12 channel mask, set 1 to a channel to mask (deactivate it)
LT13_CHMASK: LT13 channel mask, set 1 to a channel to mask (deactivate it)
LT14_CHMASK: LT14 channel mask, set 1 to a channel to mask (deactivate it)
LT15_CHMASK: LT15 channel mask, set 1 to a channel to mask (deactivate it)
LT16_CHMASK: LT16 channel mask, set 1 to a channel to mask (deactivate it)
LT17_CHMASK: LT17 channel mask, set 1 to a channel to mask (deactivate it)
LT18_CHMASK: LT18 channel mask, set 1 to a channel to mask (deactivate it)
LT19_CHMASK: LT19 channel mask, set 1 to a channel to mask (deactivate it)
LT20_CHMASK: LT20 channel mask, set 1 to a channel to mask (deactivate it)
LT21_CHMASK: LT21 channel mask, set 1 to a channel to mask (deactivate it)
LT22_CHMASK: LT22 channel mask, set 1 to a channel to mask (deactivate it)
LT23_CHMASK: LT23 channel mask, set 1 to a channel to mask (deactivate it)
LT24_CHMASK: LT24 channel mask, set 1 to a channel to mask (deactivate it)
LT_HIT_CNT_RESET: LTB Hit counter reset RESET 0x39 0xe4 0 w Pulse Write 1 to reset hit counters.
LT_HIT_CNT_SNAP: LTB Hit counter snap SNAP 0x3a 0xe8 0 rw 0x1 1 to snap the hit counters.
LT_LINK_AUTOMASK: Toggle on/off LTB Automasking LT_LINK_AUTOMASK 0x247 0x91c 0 rw 0x1 1 to enable automatic LT link masking
LT_LINK_EN0: Toggle on/off LTBs 0-9 DSI 0 RX Link Enable 0x242 0x908 [9:0] rw 0x3FF
LT_LINK_EN1: Toggle on/off LTBs 10-19 DSI 1 RX Link Enable 0x243 0x90c [9:0] rw 0x3FF
LT_LINK_EN2: Toggle on/off LTBs 20-29 DSI 2 RX Link Enable 0x244 0x910 [9:0] rw 0x3FF
LT_LINK_EN3: Toggle on/off LTBs 30-39 DSI 3 RX Link Enable 0x245 0x914 [9:0] rw 0x3FF
LT_LINK_EN4: Toggle on/off LTBs 40-49 DSI 4 RX Link Enable 0x246 0x918 [9:0] rw 0x3FF
LT_LINK_READY0: LTB link 0 available and ready to receive data
LT_LINK_READY1: LTB link 1 available and ready to receive data
LT_LINK_READY2: LTB link 2 available and ready to receive data
LT_LINK_READY3: LTB link 3 available and ready to receive data
LT_LINK_READY4: LTB link 4 available and ready to receive data
MIN_DEADTIME_MODE: Minimize deadtime by ignoring the TIU module MIN_DEADTIME_MODE 0xf 0x3c 3 rw 0x0
OUTER_TOF_THRESH: Total outer TOF (cortina + umbrella) threshhold (nhits)
PRESCALE_BYPASS: PRESCALE_BYPASS set true to ignore prescale setting PRESCALE_BYPASS 0x44 0x110 0 rw 0x0 1 to bypass prescales
RB0_CNTS: Readout counter on RB=0 CNTS_0 0xf2 0x3c8 [7:0] r Readout count on RB=0
RB1_CNTS: Readout counter on RB=1 CNTS_1 0xf2 0x3c8 [15:8] r Readout count on RB=1
RB2_CNTS: Readout counter on RB=2 CNTS_2 0xf2 0x3c8 [23:16] r Readout count on RB=2
RB3_CNTS: Readout counter on RB=3 CNTS_3 0xf2 0x3c8 [31:24] r Readout count on RB=3
RB4_CNTS: Readout counter on RB=4 CNTS_4 0xf3 0x3cc [7:0] r Readout count on RB=4
RB5_CNTS: Readout counter on RB=5 CNTS_5 0xf3 0x3cc [15:8] r Readout count on RB=5
RB6_CNTS: Readout counter on RB=6 CNTS_6 0xf3 0x3cc [23:16] r Readout count on RB=6
RB7_CNTS: Readout counter on RB=7 CNTS_7 0xf3 0x3cc [31:24] r Readout count on RB=7
RB8_CNTS: Readout counter on RB=8 CNTS_8 0xf4 0x3d0 [7:0] r Readout count on RB=8
RB9_CNTS: Readout counter on RB=9 CNTS_9 0xf4 0x3d0 [15:8] r Readout count on RB=9
RB10_CNTS: Readout counter on RB=10 CNTS_10 0xf4 0x3d0 [23:16] r Readout count on RB=10
RB11_CNTS: Readout counter on RB=11 CNTS_11 0xf4 0x3d0 [31:24] r Readout count on RB=11
RB12_CNTS: Readout counter on RB=12 CNTS_12 0xf5 0x3d4 [7:0] r Readout count on RB=12
RB13_CNTS: Readout counter on RB=13 CNTS_13 0xf5 0x3d4 [15:8] r Readout count on RB=13
RB14_CNTS: Readout counter on RB=14 CNTS_14 0xf5 0x3d4 [23:16] r Readout count on RB=14
RB15_CNTS: Readout counter on RB=15 CNTS_15 0xf5 0x3d4 [31:24] r Readout count on RB=15
RB16_CNTS: Readout counter on RB=16 CNTS_16 0xf6 0x3d8 [7:0] r Readout count on RB=16
RB17_CNTS: Readout counter on RB=17 CNTS_17 0xf6 0x3d8 [15:8] r Readout count on RB=17
RB18_CNTS: Readout counter on RB=18 CNTS_18 0xf6 0x3d8 [23:16] r Readout count on RB=18
RB19_CNTS: Readout counter on RB=19 CNTS_19 0xf6 0x3d8 [31:24] r Readout count on RB=19
RB20_CNTS: Readout counter on RB=20 CNTS_20 0xf7 0x3dc [7:0] r Readout count on RB=20
RB21_CNTS: Readout counter on RB=21 CNTS_21 0xf7 0x3dc [15:8] r Readout count on RB=21
RB22_CNTS: Readout counter on RB=22 CNTS_22 0xf7 0x3dc [23:16] r Readout count on RB=22
RB23_CNTS: Readout counter on RB=23 CNTS_23 0xf7 0x3dc [31:24] r Readout count on RB=23
RB24_CNTS: Readout counter on RB=24 CNTS_24 0xf8 0x3e0 [7:0] r Readout count on RB=24
RB25_CNTS: Readout counter on RB=25 CNTS_25 0xf8 0x3e0 [15:8] r Readout count on RB=25
RB26_CNTS: Readout counter on RB=26 CNTS_26 0xf8 0x3e0 [23:16] r Readout count on RB=26
RB27_CNTS: Readout counter on RB=27 CNTS_27 0xf8 0x3e0 [31:24] r Readout count on RB=27
RB28_CNTS: Readout counter on RB=28 CNTS_28 0xf9 0x3e4 [7:0] r Readout count on RB=28
RB29_CNTS: Readout counter on RB=29 CNTS_29 0xf9 0x3e4 [15:8] r Readout count on RB=29
RB30_CNTS: Readout counter on RB=30 CNTS_30 0xf9 0x3e4 [23:16] r Readout count on RB=30
RB31_CNTS: Readout counter on RB=31 CNTS_31 0xf9 0x3e4 [31:24] r Readout count on RB=31
RB32_CNTS: Readout counter on RB=32 CNTS_32 0xfa 0x3e8 [7:0] r Readout count on RB=32
RB33_CNTS: Readout counter on RB=33 CNTS_33 0xfa 0x3e8 [15:8] r Readout count on RB=33
RB34_CNTS: Readout counter on RB=34 CNTS_34 0xfa 0x3e8 [23:16] r Readout count on RB=34
RB35_CNTS: Readout counter on RB=35 CNTS_35 0xfa 0x3e8 [31:24] r Readout count on RB=35
RB36_CNTS: Readout counter on RB=36 CNTS_36 0xfb 0x3ec [7:0] r Readout count on RB=36
RB37_CNTS: Readout counter on RB=37 CNTS_37 0xfb 0x3ec [15:8] r Readout count on RB=37
RB38_CNTS: Readout counter on RB=38 CNTS_38 0xfb 0x3ec [23:16] r Readout count on RB=38
RB39_CNTS: Readout counter on RB=39 CNTS_39 0xfb 0x3ec [31:24] r Readout count on RB=39
RB40_CNTS: Readout counter on RB=40 CNTS_40 0xfc 0x3f0 [7:0] r Readout count on RB=40
RB41_CNTS: Readout counter on RB=41 CNTS_41 0xfc 0x3f0 [15:8] r Readout count on RB=41
RB42_CNTS: Readout counter on RB=42 CNTS_42 0xfc 0x3f0 [23:16] r Readout count on RB=42
RB43_CNTS: Readout counter on RB=43 CNTS_43 0xfc 0x3f0 [31:24] r Readout count on RB=43
RB44_CNTS: Readout counter on RB=44 CNTS_44 0xfd 0x3f4 [7:0] r Readout count on RB=44
RB45_CNTS: Readout counter on RB=45 CNTS_45 0xfd 0x3f4 [15:8] r Readout count on RB=45
RB46_CNTS: Readout counter on RB=46 CNTS_46 0xfd 0x3f4 [23:16] r Readout count on RB=46
RB47_CNTS: Readout counter on RB=47 CNTS_47 0xfd 0x3f4 [31:24] r Readout count on RB=47
RB48_CNTS: Readout counter on RB=48 CNTS_48 0xfe 0x3f8 [7:0] r Readout count on RB=48
RB49_CNTS: Readout counter on RB=49 CNTS_49 0xfe 0x3f8 [15:8] r Readout count on RB=49
RB_BLOCK_IF_BUSY_31_TO_0: Set Readoutboard BUSY behaviour RB_BLOCK_IF_BUSY_31_TO_0 0x24a 0x928 [31:0] rw 0x0 Bitmask to specify if a readout board is BUSY then do not trigger (RB slots 31:0)
RB_BLOCK_IF_BUSY_49_TO_32: Set Readoutboard BUSY behaviour RB_BLOCK_IF_BUSY_49_TO_32 0x24b 0x92c [17:0] rw 0x0 Bitmask to specify if a readout board is BUSY then do not trigger (RB slots 49:32)
RB_CNTS_RESET: Reset RB counters 0-49 RESET 0xff 0x3fc 0 w Pulse Write 1 to reset hit counters.
RB_CNTS_SNAP: Snap RB counters 0-49 SNAP 0x100 0x400 0 rw 0x1 1 to snap the hit counters.
RB_INTEGRATION_WINDOW: The RB integration window determines how long RBs should be read out after the trigger, basically the trigger window + x RB_INTEGRATION_WINDOW 0xf 0x3c [12:8] rw 0x1 Number of 100MHz clock cycles to integrate the LTB hits to determine which RBs to read out.
RB_LOST_TRIGGER_RATE: The lost trigger rate due to RB busy timeouts RB_LOST_TRIGGER_RATE 0x24c 0x930 [23:0]
RB_READ_ALL_CHANNELS: This setting is basically the ‘trace suppression mode’. When asserted, only RBs for fired LTBs in the trigger window + RB_INTEGRATION_WINDOW will be read out. RB_READ_ALL_CHANNELS 0xf 0x3c 13 rw 0x1 Set to 1 to read all channels from RB for any trigger
REQUIRE_BETA: Require beta condition for the Gaps (antiparticle) trigger REQUIRE_BETA 0x14 0x50 25 rw 0x1 Require beta in the gaps trigger
RESYNC: RESYNC 0xa 0x28 0 w Pulse Write 1 to resync This will synchronize the RB and MTB clocks and should be issued at run start.
SWAP_RB_LINK_IDS: SWAP_RB_LINK_IDS 0x247 0x91c 1 rw 0x1
TIU_BAD: Check if the TIU link is bad TIU_BAD 0xf 0x3c 0 r 1 means that the tiu link is not working
TIU_BUSY_IGNORE: Set/unset the BUSY_INGORE TIU_BUSY_IGNORE 0xf 0x3c 2 rw 0x0 1 means the the MTB should ignore the TIU busy flag (e.g. because it is stuck)
TIU_BUSY_LENGTH: The length of the tiu busy signal TIU_BUSY_LENGTH 0x11f 0x47c [31:0] r Length in 10ns cycles of the last TIU busy flag
TIU_BUSY_RATE: Rate of TIU asserting busy. Measures the fraction of time the TIU was busy. TIU_BUSY_RATE 0x254 0x950 [23:0] r
TIU_BUSY_STUCK: Check if the TIU BUSY is stuck TIU_BUSY_STUCK 0xf 0x3c 1 r 1 means the TIU has been stuck high for a long time
TIU_EMULATION_MODE: Set/Unset the TIU emulation mode TIU_EMULATION_MODE 0xe 0x38 0 rw 0x0 1 to emulate the TIU
TIU_EMU_BUSY_CNT: Read out how many clock cycles the NTB has been busy because of the TIU busy signal TIU_EMU_BUSY_CNT 0xe 0x38 [31:14] rw 0xC350 Number of 10 ns clock cyles that the emulator will remain busy
TIU_LOST_TRIGGER_RATE: The lost trigger rate due to “tracker busy” signals received by the TIU TIU_LOST_TRIGGER_RATE 0x24d 0x934 [23:0]
TIU_LT_AND_RB_MULT: Read out the whole register 0xf at once and then
TIU_TIMEOUT_CONST: Minimum enforced deadtime for TIU triggers. In units of 10 ns. A setting of 105 is the default of 1.05us. TIU_TIMEOUT_CNT 0x255 0x954 [19:0] rw
TIU_USE_AUX_LINK: Choose between the 2 different TIU links 1 for J11, 0 for J3 0xe 0x38 1 rw 0x0 1 to use J11; 0 to use J3
TOTAL_TOF_THRESH: Total TOF (cube + cortina + umbrella) threshhold (nhits)
TRACK_CENTRAL_BLOCKED_RATE: Rate of Track Central trigger blocked due precaler disable TRACK_CENTRAL_BLOCKED_RATE 0x252 0x948 [23:0] r
TRACK_CENTRAL_IS_GLOBAL: Add the central track trigger to all triggers TRACK_CENTRAL_IS_GLOBAL 0xb 0x2c 2 rw 0x0 1 makes the TRACK central read all paddles.
TRACK_CENTRAL_PRESCALE: The central track trigger requires hits in the Umbrella and upper cube. Can be used with a prescale factor. If the prescale is 0, then it will be disabled TRACK_CENTRAL_PRESCALE 0x42 0x108 [31:0] rw 0x0 Prescale value for the Umbrella + Cube Top Track Trigger. 0 == 0% (off), 2**32-1 == 100%
TRACK_TRIGGER_BLOCKED_RATE: Rate of Track trigger blocked due to prescaler of disable TRACK_TRIGGER_BLOCKED_RATE 0x250 0x940 [23:0] r Rate of this trigger blocked due to prescaler or disable
TRACK_TRIG_IS_GLOBAL: Add the track trigger to all triggers TRACE_TRIG_IS_GLOBAL 0xb 0x2c 1 rw 0x0
TRACK_TRIG_PRESCALE: More strict condition, requiring a track pattern. Can be used with a prescale factor. If the prescale is 0, then it will be disabled TRACK_TRIGGER_PRESCALE 0x41 0x104 [31:0] rw 0x0 Prescale value for the Inner + Outer Track Trigger. 0 == 0% (off), 2**32-1 == 100%
TRACK_UMB_CENTRAL_BLOCKED_RATE: Rate of Track Umbrella Central trigger blocked due to prescaler or disable TRACK_UMB_CENTRAL_BLOCKED_RATE 0x253 0x94c [23:0] r
TRACK_UMB_CENTRAL_IS_GLOBAL: Add the umbrella central track trigger to all triggers TRACK_UMB_CENTRAL_IS_GLOBAL 0xb 0x2c 3 rw 0x0 1 makes the TRACK UMB central read all paddles.
TRACK_UMB_CENTRAL_PRESCALE: Prescale factor for the CENTRAL UMBRELLA TRACK trigger TRACK_UMB_CENTRAL_PRESCALE 0x249 0x924 [31:0] rw 0x0 Prescale value for the Umbrella Center + Cube Top Track Trigger. 0 == 0% (off), 2**32-1 == 100%
TRG_LOST_TRIGGER_RATE: Rate of lost triggers due to MTB internal trigger block deadtime (in Hz) TRG_LOST_TRIGGER_RATE 0x24e 0x938 [23:0] r
TRIGGER_RATE: The global trigger rate in Hz TRIGGER_RATE 0x17 0x5c [23:0] r Rate of triggers in Hz
TRIG_CYCLIC_EN: Enable cyclic trigger TRIG_CYCLIC_EN 0x240 0x900 0 rw 0x0
TRIG_CYCLIC_INTERVAL: Set cyclic trigger interval (in # clock cycles, 1 clock cycle ~ 10 ns) TRIG_CYCLIC_INTERVAL 0x241 0x904 [31:0] rw 0x0
TRIG_GEN_RATE: TRIG_GEN_RATE 0x9 0x24 [31:0] rw 0x0 Rate of generated triggers f_trig = (1/clk_period) * rate/0xffffffff Set a random forced trigger
UMBRELLA_CENTER_THRESH: Set the (nhit) threshold for the umbrealla center
UMBRELLA_THRESH: Set the (nhit) threshold for the cube bottom panesl

Functions§

prescale_to_u32: The prescale values are defined by a single u32 This number represents 0 for trigger off and 1.0 for 2**32 - 1 (which is u32::MAX)

Module registers

Module registers Copy item path

Structs§

Constants§

Functions§

Module registers