gondola_core/tof/master_trigger/registers.rs
1//! MasterTriggerBoard registers
2//!
3//! This should be the same as the reference
4//! doucmentation on the [UCLA gitlab server](https://gitlab.com/ucla-gaps-tof/firmware/-/blob/master/regmap/mt_address_table.org?ref_type=heads)
5//!
6//! <div class="warning"> This currently does NOT sync itself with the reposity, so we have to take extra care that these numbers are correct!.</div>
7//!
8//! All registers are 32bit
9
10use std::error::Error;
11use std::fmt;
12use crate::io::ipbus::IPBus;
13
14/// The prescale values are defined by a single u32
15/// This number represents 0 for trigger off and
16/// 1.0 for 2**32 - 1 (which is u32::MAX)
17///
18/// The range for the prescale value is [0,1.0].
19/// If the given value is outside of the interval
20/// boundaries, it will be converted to the next
21/// interval limit
22pub fn prescale_to_u32(mut prescale : f32) -> u32 {
23 if prescale > 1.0 {
24 warn!("Prescale value > 1.0 will be converted to 1.0!");
25 prescale = 1.0
26 }
27 if prescale < 0.0 {
28 prescale = 0.0
29 }
30 // converion
31 ((u32::MAX as f32) * prescale).floor() as u32
32}
33
34
35/// A single 32bit register on the MTB with an
36/// associated mask to mask parts of ig
37pub struct MTBRegister<'a> {
38 /// the address of the register on the MTB
39 /// (not Addr8)
40 pub addr : u32,
41 /// Some registers on the MTB share functionality, which
42 /// we are splitting in different MTBRegisters. So even
43 /// if two MTBRegisters share the same address, they
44 /// might have a different mask to achieve different
45 /// things and will thus have a different name.
46 pub mask : u32,
47 /// Description about what is achieved when setting
48 /// this register?
49 pub descr : &'a str,
50 /// Is this register shared with other values? In that
51 /// case we need to do a rmw operation instead of
52 /// writing
53 pub rmw : bool,
54 /// This register is only read-only (e.g. providing
55 /// a monitoring value
56 pub ro : bool,
57 /// This register is "pulse" type. So it can be
58 /// asserted, but there is no point in reading it
59 /// out, since it will reset itself.
60 pub pulse : bool,
61}
62
63impl MTBRegister<'_> {
64
65 /// Set the register to desired value
66 pub fn set(&self, bus : &mut IPBus, value : u32)
67 -> Result<(), Box<dyn Error>> {
68 //println!("Settting {}", self);
69 if self.rmw {
70 self.rmw(bus, value)?;
71 }
72 else {
73 self.write(bus, value)?;
74 }
75 // this can be used for debugging
76 // (print back the value)
77 //let rv = self.read_all(bus)?;
78 //println!("Register reads {:x} {} {:x} after write ops!", self.addr, self.descr, rv);
79 Ok(())
80 }
81
82 /// Get the value this register is set to
83 pub fn get(&self, bus : &mut IPBus)
84 -> Result<u32, Box<dyn Error>> {
85 //FIXME - error type
86 //if self.pulse {
87 // return(Err)
88 //}
89 let rv = self.read(bus)?;
90 //if self.addr != 0x13 && self.addr != 0x11 {
91 // //
92 // //println!("Register reads {:x} {} {:x}!", self.addr, self.descr, rv);
93 //}
94 Ok(rv)
95 }
96
97
98 // FIXME - basically whenever we have a amsk
99 // != u32::MAX we need rmw
100 fn write(&self, bus : &mut IPBus, value : u32)
101 -> Result<(), Box<dyn Error>> {
102 let masked_value = self.mask & value;
103 //println!("Writing ... {:x}", masked_value);
104 Ok(bus.write(self.addr, masked_value)?)
105 }
106
107 fn read_all(&self, bus : &mut IPBus)
108 -> Result<u32, Box<dyn Error>> {
109 let value = bus.read(self.addr)?;
110 Ok(value)
111 }
112
113 fn read(&self, bus : &mut IPBus)
114 -> Result<u32, Box<dyn Error>> {
115 let mut value = bus.read(self.addr)?;
116 value = value & self.mask;
117 //println!("Read all .. {:?}", self.read_all(bus));
118 if self.mask > 255 {
119 //println!("...shifting by {}", self.mask.trailing_zeros());
120 value = value >> self.mask.trailing_zeros();
121 }
122 Ok(value)
123 }
124
125 /// Read-modify-write
126 fn rmw(&self, bus : &mut IPBus, value : u32)
127 -> Result<(), Box<dyn Error>> {
128 let mut data = self.read_all(bus)?;
129 //println!("step 1 ..{}",data);
130 // leave everything else the same, but zero out
131 // the masked part
132 data = data & !self.mask;
133 //println!("step 2 ..{}",data);
134 // reset the masked part and write again
135 //println!("step 3 ..{}", value << self.mask.trailing_zeros());
136 data = data | (value << self.mask.trailing_zeros());
137 //println!("step 4 ..{}",data);
138 Ok(bus.write(self.addr, data)?)
139 }
140}
141
142impl fmt::Display for MTBRegister<'_> {
143 fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
144 let mut rmw_str = "R/W";
145 if self.rmw {
146 rmw_str = "R/RMW"
147 }
148 if self.ro {
149 rmw_str = "RO"
150 }
151 if self.pulse {
152 rmw_str = "pulse"
153 }
154 let mut repr = format!("<MTBRegister [{}]:", rmw_str);
155 repr += &(format!("\n address : {:x}" , self.addr));
156 repr += &(format!("\n mask : {:x}" , self.mask));
157 repr += &(format!("\n descr : {}>", self.descr));
158 write!(f, "{}", repr)
159 }
160}
161
162/////////////////////////////////////////////////////////////////////
163
164/////////////////////////////////////////////////////////////////////
165
166// Module MT adr = 0x0
167//
168// Implements various control and monitoring functions of the DRS Logic
169
170///Prescale value for the GAPS trigger. 0 == 0% (off), 2**32-1 == 100%
171/// GAPS_TRIG_PRESCALE 0x248 0x920 \[31:0\] rw 0xffffffff
172pub const GAPS_TRIG_PRESCALE : MTBRegister<'static> = MTBRegister {
173 addr : 0x248,
174 mask : 0xffffffff,
175 descr : "Prescale value for the GAPS trigger. 0 == 0% (off), 2**32-1 == 100%",
176 rmw : true,
177 ro : false,
178 pulse : false,
179};
180
181
182/// Force a trigger (has to be previously set)
183/// FORCE_TRIGGER 0x8 0x20 0 w Pulse Write 1 to generate a trigger
184pub const FORCE_TRIGGER : MTBRegister<'static> = MTBRegister {
185 addr : 0x8,
186 mask : 0xffffffff,
187 descr : "Force the readout and issue a one-time trigger",
188 rmw : false,
189 ro : false,
190 pulse : true,
191};
192
193///// TIU_USE_AUX_LINK 0xe 0x38 1 rw 0x0 1 to use J11; 0 to use J3
194/// Check if the TIU link is bad
195/// TIU_BAD 0xf 0x3c 0 r 1 means that the tiu link is not working
196pub const TIU_BAD : MTBRegister<'static> = MTBRegister {
197 addr : 0xf,
198 mask : 0x00000001,
199 descr : "Check if the TIU link is bad",
200 rmw : false,
201 ro : true,
202 pulse : false
203};
204
205/// Read out how many clock cycles the NTB has been busy because of the TIU busy signal
206/// TIU_EMU_BUSY_CNT 0xe 0x38 \[31:14\] rw 0xC350 Number of 10 ns clock cyles that the emulator will remain busy
207pub const TIU_EMU_BUSY_CNT : MTBRegister<'static> = MTBRegister {
208 addr : 0xe,
209 mask : 0xffffc000,
210 descr : "Read out emulated TIU busy time (in 10ns clock cycles)",
211 rmw : true,
212 ro : false,
213 pulse : false
214};
215
216/// Enable cyclic trigger
217/// TRIG_CYCLIC_EN 0x240 0x900 0 rw 0x0
218pub const TRIG_CYCLIC_EN : MTBRegister<'static> = MTBRegister {
219 addr : 0x240,
220 mask : 0x00000001,
221 descr : "Enable the use of a cyclic trigger",
222 rmw : true,
223 ro : false,
224 pulse : false
225};
226
227/// Set cyclic trigger interval (in # clock cycles, 1 clock cycle ~ 10 ns)
228/// TRIG_CYCLIC_INTERVAL 0x241 0x904 \[31:0\] rw 0x0
229pub const TRIG_CYCLIC_INTERVAL : MTBRegister<'static> = MTBRegister {
230 addr : 0x241,
231 mask : 0xffffffff,
232 descr : "Set the cyclic trigger interval in # clock cycles (int only) --> ie if desire trigger every 20 nsec, set interval = 2",
233 rmw : true,
234 ro : false,
235 pulse : false
236};
237
238/// Toggle on/off LTBs 0-9
239/// DSI 0 RX Link Enable 0x242 0x908 \[9:0\] rw 0x3FF
240pub const LT_LINK_EN0 : MTBRegister<'static> = MTBRegister {
241 addr : 0x242,
242 mask : 0x000003ff,
243 descr : "Enable DSI link for LTBs 0-9",
244 rmw : true,
245 ro : false,
246 pulse : false
247};
248/// Toggle on/off LTBs 10-19
249/// DSI 1 RX Link Enable 0x243 0x90c \[9:0\] rw 0x3FF
250pub const LT_LINK_EN1 : MTBRegister<'static> = MTBRegister {
251 addr : 0x243,
252 mask : 0x000003ff,
253 descr : "Enable DSI link for LTBs 10-19",
254 rmw : true,
255 ro : false,
256 pulse : false
257};
258/// Toggle on/off LTBs 20-29
259/// DSI 2 RX Link Enable 0x244 0x910 \[9:0\] rw 0x3FF
260pub const LT_LINK_EN2 : MTBRegister<'static> = MTBRegister {
261 addr : 0x244,
262 mask : 0x000003ff,
263 descr : "Enable DSI link for LTBs 20-29",
264 rmw : true,
265 ro : false,
266 pulse : false
267};
268/// Toggle on/off LTBs 30-39
269/// DSI 3 RX Link Enable 0x245 0x914 \[9:0\] rw 0x3FF
270pub const LT_LINK_EN3 : MTBRegister<'static> = MTBRegister {
271 addr : 0x245,
272 mask : 0x000003ff,
273 descr : "Enable DSI link for LTBs 30-39",
274 rmw : true,
275 ro : false,
276 pulse : false
277};
278/// Toggle on/off LTBs 40-49
279/// DSI 4 RX Link Enable 0x246 0x918 \[9:0\] rw 0x3FF
280pub const LT_LINK_EN4 : MTBRegister<'static> = MTBRegister {
281 addr : 0x246,
282 mask : 0x000003ff,
283 descr : "Enable DSI link for LTBs 40-49",
284 rmw : true,
285 ro : false,
286 pulse : false
287};
288///Toggle on/off LTB Automasking
289/// LT_LINK_AUTOMASK 0x247 0x91c 0 rw 0x1
290/// 1 to enable automatic LT link masking
291pub const LT_LINK_AUTOMASK : MTBRegister<'static> = MTBRegister {
292 addr : 0x247,
293 mask : 0x00000001,
294 descr : "Enable LT Automasking -> 1 to enable LTB link masking",
295 rmw : true,
296 ro : false,
297 pulse : false,
298};
299
300/// Set/Unset the TIU emulation mode
301/// TIU_EMULATION_MODE 0xe 0x38 0 rw 0x0 1 to emulate the TIU
302pub const TIU_EMULATION_MODE : MTBRegister<'static> = MTBRegister {
303 addr : 0xe,
304 mask : 0x00000001,
305 descr : "Set/Unset the TIU emulation mode",
306 rmw : true,
307 ro : false,
308 pulse : false
309};
310
311/// The length of the tiu busy signal
312/// TIU_BUSY_LENGTH 0x11f 0x47c \[31:0\] r Length in 10ns cycles of the last TIU busy flag
313pub const TIU_BUSY_LENGTH : MTBRegister<'static> = MTBRegister {
314 addr : 0x11f,
315 mask : 0xffffffff,
316 descr : "The length of the tiu busy signal in clock cycles [10ns/cycle]",
317 rmw : false,
318 ro : true,
319 pulse : false
320};
321
322/// Read out the whole register 0xf at once and then
323pub const TIU_LT_AND_RB_MULT : MTBRegister<'static> = MTBRegister {
324 addr : 0xf,
325 mask : 0x3fff,
326 descr : "Aggregated TIU, LT and RB general information",
327 rmw : false,
328 ro : true,
329 pulse : false
330};
331
332/// Check if the TIU BUSY is stuck
333/// TIU_BUSY_STUCK 0xf 0x3c 1 r 1 means the TIU has been stuck high for a long time
334pub const TIU_BUSY_STUCK : MTBRegister<'static> = MTBRegister {
335 addr : 0xf,
336 mask : 0x2,
337 descr : "Tiu busy stuck high",
338 rmw : false,
339 ro : true,
340 pulse : false
341};
342
343/// Set/unset the BUSY_INGORE
344/// TIU_BUSY_IGNORE 0xf 0x3c 2 rw 0x0 1 means the the MTB should ignore the TIU busy flag (e.g. because it is stuck)
345pub const TIU_BUSY_IGNORE : MTBRegister<'static> = MTBRegister {
346 addr : 0xf,
347 mask : 0x4,
348 descr : "Ignore the tiu busy signal",
349 rmw : true,
350 ro : false,
351 pulse : false,
352};
353
354
355/// The global event id
356/// EVENT_CNT 0xd 0x34 \[31:0\] r Event Counter
357pub const EVENT_CNT : MTBRegister<'static> = MTBRegister {
358 addr : 0xd,
359 mask : 0xffffffff,
360 descr : "Global event counter",
361 rmw : false,
362 ro : true,
363 pulse : false
364};
365
366/// Reset the global event id (excecute with caution)
367/// EVENT_CNT_RESET 0xc 0x30 0 w Pulse Write 1 to reset the event counter
368pub const EVENT_CNT_RESET : MTBRegister<'static> = MTBRegister {
369 addr : 0xc,
370 mask : 0x1,
371 descr : "Reset the event ID",
372 rmw : false,
373 ro : false,
374 pulse : true
375};
376
377/// The RB integration window determines how long RBs should be read out
378/// after the trigger, basically the trigger window + x
379/// RB_INTEGRATION_WINDOW 0xf 0x3c \[12:8\] rw 0x1 Number of 100MHz clock cycles to integrate the LTB hits to determine which RBs to read out.
380pub const RB_INTEGRATION_WINDOW : MTBRegister<'static> = MTBRegister {
381 addr : 0xf,
382 mask : 0x00000f00,
383 descr : "Determine how long RBs should be read out after the trigger. Default 1.",
384 rmw : true,
385 ro : false,
386 pulse : false,
387};
388
389/// This setting is basically the 'trace suppression mode'. When asserted, only RBs for
390/// fired LTBs in the trigger window + RB_INTEGRATION_WINDOW will be read out.
391/// RB_READ_ALL_CHANNELS 0xf 0x3c 13 rw 0x1 Set to 1 to read all channels from RB for any trigger
392pub const RB_READ_ALL_CHANNELS : MTBRegister<'static> = MTBRegister {
393 addr : 0xf,
394 mask : 0x00002000,
395 descr : "Enable/Disable trace suppression mode. 1 = Enable",
396 rmw : true,
397 ro : false,
398 pulse : false,
399};
400
401/// Set Readoutboard BUSY behaviour
402/// RB_BLOCK_IF_BUSY_31_TO_0 0x24a 0x928 \[31:0\] rw 0x0 Bitmask to specify if a readout board is BUSY then do not trigger (RB slots 31:0)
403pub const RB_BLOCK_IF_BUSY_31_TO_0 : MTBRegister<'static> = MTBRegister {
404 addr : 0x24a,
405 mask : 0xffffffff,
406 descr : "Define if triggers should suppressed if RBs are busy. 1 bit per board",
407 rmw : false,
408 ro : false,
409 pulse : false,
410};
411
412/// Set Readoutboard BUSY behaviour
413/// RB_BLOCK_IF_BUSY_49_TO_32 0x24b 0x92c \[17:0\] rw 0x0 Bitmask to specify if a readout board is BUSY then do not trigger (RB slots 49:32)
414pub const RB_BLOCK_IF_BUSY_49_TO_32 : MTBRegister<'static> = MTBRegister {
415 addr : 0x24b,
416 mask : 0x0003ffff,
417 descr : "Define if triggers should suppressed if RBs are busy. 1 bit per board",
418 rmw : false,
419 ro : false,
420 pulse : false,
421};
422
423
424// MT.EVENT_QUEUE
425// DAQ Buffer
426
427/// Reset the DAQ buffer (this does NOT reset the event ID)
428/// RESET 0x10 0x40 0 w Pulse DAQ Buffer Reset
429pub const EVQ_RESET : MTBRegister<'static> = MTBRegister {
430 addr : 0x10,
431 mask : 0x00000001,
432 descr : "Reset the DAQ buffer event queue! Will not reset event ID",
433 rmw : false,
434 ro : false,
435 pulse : true,
436};
437
438/// The DAQ buffer is full
439/// FULL 0x12 0x48 0 r DAQ Buffer Full
440pub const EVQ_FULL : MTBRegister<'static> = MTBRegister {
441 addr : 0x12,
442 mask : 0x1,
443 descr : "Read FULL bit of the MT.EVENT_QUEUE",
444 rmw : false,
445 ro : true,
446 pulse : false,
447};
448
449/// The DAQ buffer is empty
450/// FULL 0x12 0x48 1 r DAQ Buffer Full
451pub const EVQ_EMPTY : MTBRegister<'static> = MTBRegister {
452 addr : 0x12,
453 mask : 0x2,
454 descr : "Read EMPTY bit of the MT.EVENT_QUEUE",
455 rmw : false,
456 ro : true,
457 pulse : false,
458};
459
460/// DAQ data payload. An event will be broken down into
461/// multiple u32, which wlll be all accessible through
462/// this register. The EVQ_SIZE register tells how many
463/// times this register hast to be read (the actual value
464/// is twice this number, since internally the MTB operates
465/// on 16bit registers)
466/// DATA 0x11 0x44 \[31:0\] r DAQ Read Data
467pub const EVQ_DATA : MTBRegister<'static> = MTBRegister {
468 addr : 0x11,
469 mask : 0xffffffff,
470 descr : "DAQ data payload field",
471 rmw : false,
472 ro : true,
473 pulse : false
474};
475
476/// DAQ data queue SIZE. This stores twice the number of
477/// times the EVQ_DATA register has to be read out to
478/// obtain a complete event
479/// SIZE 0x13 0x4c \[31:16\] r DAQ Buffer Head Event Size
480pub const EVQ_SIZE : MTBRegister<'static> = MTBRegister {
481 addr : 0x13,
482 mask : 0xffff0000,
483 descr : "DAQ buffer data queue size in 16bit words",
484 rmw : false,
485 ro : true,
486 pulse : false,
487};
488
489/// DAQ buffer size (in events)
490/// NUM_EVENTS 0x13 0x4c \[13:0\] r DAQ Buffer Number of Event
491pub const EVQ_NUM_EVENTS : MTBRegister<'static> = MTBRegister {
492 addr : 0x13,
493 mask : 0x0003fff,
494 descr : "Number of events in DAQ buffer event queue",
495 rmw : false,
496 ro : true,
497 pulse : false,
498};
499
500//FULL 0x12 0x48 0 r DAQ Buffer Full
501//EMPTY 0x12 0x48 1 r DAQ Buffer Empty
502
503/// Any 2 paddle combination. Can be used with a prescale
504/// factor. If the prescale is 0, then it will be disabled
505/// ANY_TRIG_PRESCALE 0x40 0x100 \[31:0\] rw 0x0 Prescale value for the ANY trigger. 0 == 0% (off), 2**32-1 == 100%
506pub const ANY_TRIG_PRESCALE : MTBRegister<'static> = MTBRegister {
507 addr : 0x40,
508 mask : 0xffffffff,
509 descr : "Set the any trigger with a prescale factor. Prescale of 0 means disabled",
510 rmw : false,
511 ro : false,
512 pulse : false
513};
514
515/// More strict condition, requiring a track pattern. Can
516/// be used with a prescale factor.
517/// If the prescale is 0, then it will be disabled
518/// TRACK_TRIGGER_PRESCALE 0x41 0x104 \[31:0\] rw 0x0 Prescale value for the Inner + Outer Track Trigger. 0 == 0% (off), 2**32-1 == 100%
519pub const TRACK_TRIG_PRESCALE : MTBRegister<'static> = MTBRegister {
520 addr : 0x41,
521 mask : 0xffffffff,
522 descr : "Set the track trigger with a prescale factor. Prescale of 0 means disabled",
523 rmw : false,
524 ro : false,
525 pulse : false
526};
527
528/// The central track trigger requires hits in the Umbrella and upper cube.
529/// Can be used with a prescale factor.
530/// If the prescale is 0, then it will be disabled
531/// TRACK_CENTRAL_PRESCALE 0x42 0x108 \[31:0\] rw 0x0 Prescale value for the Umbrella + Cube Top Track Trigger. 0 == 0% (off), 2**32-1 == 100%
532pub const TRACK_CENTRAL_PRESCALE : MTBRegister<'static> = MTBRegister {
533 addr : 0x42,
534 mask : 0xffffffff,
535 descr : "Set the central track trigger with a prescale factor. Prescale of 0 means disabled",
536 rmw : false,
537 ro : false,
538 pulse : false
539};
540
541/// Prescale factor for the CENTRAL UMBRELLA TRACK trigger
542/// TRACK_UMB_CENTRAL_PRESCALE 0x249 0x924 \[31:0\] rw 0x0 Prescale value for the Umbrella Center + Cube Top Track Trigger. 0 == 0% (off), 2**32-1 == 100%
543pub const TRACK_UMB_CENTRAL_PRESCALE : MTBRegister<'static> = MTBRegister {
544 addr : 0x249,
545 mask : 0xffffffff,
546 descr : "Set the umbrella central track trigger with a prescale factor. Prescale of 0 means disabled",
547 rmw : false,
548 ro : false,
549 pulse : false
550};
551
552//Implements various control and monitoring functions of the DRS Logic
553
554/// Total inner tof (cube) threshold (nhits)
555///
556/// <div class="warning"> This setting is shared between the triggers and can impact performance of the pre-implmented triggers!!</div>
557///
558/// INNER_TOF_THRESH 0x14 0x50 \[7:0\] rw 0x3 Inner TOF hit threshold
559pub const INNER_TOF_THRESH : MTBRegister<'static> = MTBRegister {
560 addr : 0x14,
561 mask : 0x000000ff,
562 descr : "Set the nhit threshold for the inner TOF (cube)",
563 rmw : true,
564 ro : false,
565 pulse : false
566};
567
568
569/// Total outer TOF (cortina + umbrella) threshhold (nhits)
570///
571/// <div class="warning"> This setting is shared between the triggers and can impact performance of the pre-implmented triggers!!</div>
572///
573/// OUTER_TOF_THRESH 0x14 0x50 \[15:8\] rw 0x3 Outer TOF hit threshold
574pub const OUTER_TOF_THRESH : MTBRegister<'static> = MTBRegister {
575 addr : 0x14,
576 mask : 0x0000ff00,
577 descr : "Set the nhit threshold for the outer TOF (cube)",
578 rmw : true,
579 ro : false,
580 pulse : false
581};
582
583
584/// Total TOF (cube + cortina + umbrella) threshhold (nhits)
585///
586/// <div class="warning"> This setting is shared between the triggers and can impact performance of the pre-implmented triggers!!</div>
587///
588/// TOTAL_TOF_THRESH 0x14 0x50 \[23:16\] rw 0x8 Total TOF hit threshold
589pub const TOTAL_TOF_THRESH : MTBRegister<'static> = MTBRegister {
590 addr : 0x14,
591 mask : 0x00ff0000,
592 descr : "Set the nhit threshold for the entire TOF (nhit)",
593 rmw : true,
594 ro : false,
595 pulse : false
596};
597
598/// Enable the Gaps (antiparticle) trigger
599/// GAPS_TRIGGER_EN 0x14 0x50 24 rw 0x0 Enable the gaps trigger.
600pub const GAPS_TRIGGER_EN : MTBRegister<'static> = MTBRegister {
601 addr : 0x14,
602 mask : 0x01000000,
603 descr : "Set the GAPS antiparticle trigger (on/off)",
604 rmw : true,
605 ro : false,
606 pulse : false
607};
608
609
610/// Require beta condition for the Gaps (antiparticle) trigger
611/// REQUIRE_BETA 0x14 0x50 25 rw 0x1 Require beta in the gaps trigger
612pub const REQUIRE_BETA : MTBRegister<'static> = MTBRegister {
613 addr : 0x14,
614 mask : 0x02000000,
615 descr : "Enable beta condition for the Gaps (antiparticle) trigger",
616 rmw : true,
617 ro : false,
618 pulse : false
619};
620
621/// Enable the configurable trigger (has to be enable for any fine-grained threshhold
622/// setting to come into effect)
623/// CONFIGURABLE_TRIGGER_EN 0x14 0x50 31 rw 0x0 Enable the configurable trigger
624pub const CONFIGURABLE_TRIGGER_EN : MTBRegister<'static> = MTBRegister {
625 addr : 0x14,
626 mask : 0x10000000,
627 descr : "Enable the configurable trigger. This allows to use the individual thresholds",
628 rmw : true,
629 ro : false,
630 pulse : false,
631};
632
633
634/// Set the (nhit) threshold for the cube side panesl
635///
636/// <div class="warning"> Requires the configurable trigger to be enabled!</div>
637///
638/// CUBE_SIDE_THRESH 0x15 0x54 \[7:0\] rw 0x0 Threshold for the hit bitmap. Threshold must be > this number.
639pub const CUBE_SIDE_THRESH : MTBRegister<'static> = MTBRegister {
640 addr : 0x15,
641 mask : 0x000000ff,
642 descr : "Set the nhit threshold for the cube sides. Needs configurable trigger enabled to be in effect.",
643 rmw : true,
644 ro : false,
645 pulse : false
646};
647
648/// Set the (nhit) threshold for the cube top panesl
649///
650/// <div class="warning"> Requires the configurable trigger to be enabled!</div>
651///
652/// CUBE_TOP_THRESH 0x15 0x54 \[15:8\] rw 0x0 Threshold for the hit bitmap. Threshold must be > this number.
653pub const CUBE_TOP_THRESH : MTBRegister<'static> = MTBRegister {
654 addr : 0x15,
655 mask : 0x0000ff00,
656 descr : "Set the nhit threshold for the cube top. Needs configurable trigger enabled to be in effect.",
657 rmw : true,
658 ro : false,
659 pulse : false
660};
661
662/// Set the (nhit) threshold for the cube bottom panesl
663///
664/// <div class="warning"> Requires the configurable trigger to be enabled!</div>
665///
666/// CUBE_BOT_THRESH 0x15 0x54 \[23:16\] rw 0x0 Threshold for the hit bitmap. Threshold must be > this number.
667pub const CUBE_BOT_THRESH : MTBRegister<'static> = MTBRegister {
668 addr : 0x15,
669 mask : 0x00ff0000,
670 descr : "Set the nhit threshold for the cube top. Needs configurable trigger enabled to be in effect.",
671 rmw : true,
672 ro : false,
673 pulse : false
674};
675
676
677/// Set the (nhit) threshold for the cube bottom panesl
678///
679/// <div class="warning"> Requires the configurable trigger to be enabled!</div>
680///
681/// CUBE_CORNER_THRESH 0x15 0x54 \[31:24\] rw 0x0 Threshold for the hit bitmap. Threshold must be > this number.
682pub const CUBE_CORNER_THRESH : MTBRegister<'static> = MTBRegister {
683 addr : 0x15,
684 mask : 0xff000000,
685 descr : "Set the nhit threshold for the cube corners. Needs configurable trigger enabled to be in effect.",
686 rmw : true,
687 ro : false,
688 pulse : false
689};
690
691/// Set the (nhit) threshold for the cube bottom panesl
692///
693/// <div class="warning"> Requires the configurable trigger to be enabled!</div>
694///
695/// UMBRELLA_THRESH 0x16 0x58 \[7:0\] rw 0x0 Threshold for the hit bitmap. Threshold must be > this number.
696pub const UMBRELLA_THRESH : MTBRegister<'static> = MTBRegister {
697 addr : 0x16,
698 mask : 0x000000ff,
699 descr : "Set the nhit threshold for the complete umbrella. Needs configurable trigger enabled to be in effect.",
700 rmw : true,
701 ro : false,
702 pulse : false
703};
704
705/// Set the (nhit) threshold for the umbrealla center
706///
707/// <div class="warning"> Requires the configurable trigger to be enabled!</div>
708///
709/// UMBRELLA_CENTER_THRESH 0x16 0x58 \[15:8\] rw 0x0 Threshold for the hit bitmap. Threshold must be > this number.
710pub const UMBRELLA_CENTER_THRESH : MTBRegister<'static> = MTBRegister {
711 addr : 0x16,
712 mask : 0x0000ff00,
713 descr : "Set the nhit threshold for the umbrella center. Needs configurable trigger enabled to be in effect.",
714 rmw : true,
715 ro : false,
716 pulse : false
717};
718
719/// Set the (nhit) threshold for the cortina panesl
720///
721/// <div class="warning"> Requires the configurable trigger to be enabled!</div>
722///
723/// CORTINA_THRESH 0x16 0x58 \[23:16\] rw 0x0 Threshold for the hit bitmap. Threshold must be > this number.
724pub const CORTINA_THRESH : MTBRegister<'static> = MTBRegister {
725 addr : 0x16,
726 mask : 0x00ff0000,
727 descr : "Set the nhit threshold for the cortina. Needs configurable trigger enabled to be in effect.",
728 rmw : true,
729 ro : false,
730 pulse : false
731};
732
733/// Set the (nhit) threshold for the cortina panesl
734///
735/// <div class="warning"> Requires the configurable trigger to be enabled!</div>
736///
737/// LOST_TRIGGER_RATE 0x18 0x60 \[23:0\] r Rate of lost triggers in Hz
738pub const LOST_TRIGGER_RATE : MTBRegister<'static> = MTBRegister {
739 addr : 0x18,
740 mask : 0x00ffffff,
741 descr : "Get lost trigger rate in Hz",
742 rmw : false,
743 ro : true,
744 pulse : false
745};
746
747
748/// The lost trigger rate due to "tracker busy" signals
749/// received by the TIU
750/// TIU_LOST_TRIGGER_RATE 0x24d 0x934 \[23:0\]
751pub const TIU_LOST_TRIGGER_RATE : MTBRegister<'static> = MTBRegister {
752 addr : 0x24d,
753 mask : 0x00ffffff,
754 descr : "Get tiu lost trigger rate in Hz",
755 rmw : false,
756 ro : true,
757 pulse : false
758};
759
760/// The lost trigger rate due to RB busy timeouts
761/// RB_LOST_TRIGGER_RATE 0x24c 0x930 \[23:0\]
762pub const RB_LOST_TRIGGER_RATE : MTBRegister<'static> = MTBRegister {
763 addr : 0x24c,
764 mask : 0x00ffffff,
765 descr : "Get RB lost trigger rate in Hz",
766 rmw : false,
767 ro : true,
768 pulse : false
769};
770
771//Node Adr Adr8 Bits Perm Def Description
772//HIT_THRESH 0x14 0x50 [29:28] rw 0x0 Threshold for the hit bitmap. Threshold must be > this number.
773
774/// The global trigger rate in Hz
775/// TRIGGER_RATE 0x17 0x5c \[23:0\] r Rate of triggers in Hz
776pub const TRIGGER_RATE : MTBRegister<'static> = MTBRegister {
777 addr : 0x17,
778 mask : 0x00ffffff,
779 descr : "Get the global trigger rate in Hz",
780 rmw : false,
781 ro : true,
782 pulse : false,
783};
784
785// LTB Hit counter readout
786// MT.HIT_COUNTERS
787//
788// Counters
789
790/// LTB link 0 available and ready to receive data
791//LT_LINK_READY0 0x1a 0x68 \[9:0\] r DSI 0 RX Link OK
792pub const LT_LINK_READY0 : MTBRegister<'static> = MTBRegister {
793 addr : 0x1a,
794 mask : 0x1ff,
795 descr : "LT link 0 ready",
796 rmw : false,
797 ro : true,
798 pulse : false,
799};
800
801/// LTB link 1 available and ready to receive data
802//LT_LINK_READY1 0x1b 0x6c \[9:0\] r DSI 1 RX Link OK
803pub const LT_LINK_READY1 : MTBRegister<'static> = MTBRegister {
804 addr : 0x1b,
805 mask : 0x1ff,
806 descr : "LT link 1 ready",
807 rmw : false,
808 ro : true,
809 pulse : false,
810};
811
812/// LTB link 2 available and ready to receive data
813//LT_LINK_READY2 0x1c 0x70 \[9:0\] r DSI 2 RX Link OK
814pub const LT_LINK_READY2 : MTBRegister<'static> = MTBRegister {
815 addr : 0x1c,
816 mask : 0x1ff,
817 descr : "LT link 2 ready",
818 rmw : false,
819 ro : true,
820 pulse : false,
821};
822
823/// LTB link 3 available and ready to receive data
824//LT_LINK_READY3 0x1d 0x74 \[9:0\] r DSI 3 RX Link OK
825pub const LT_LINK_READY3 : MTBRegister<'static> = MTBRegister {
826 addr : 0x1d,
827 mask : 0x1ff,
828 descr : "LT link 3 ready",
829 rmw : false,
830 ro : true,
831 pulse : false,
832};
833
834/// LTB link 4 available and ready to receive data
835//LT_LINK_READY4 0x1e 0x78 \[9:0\] r DSI 4 RX Link OK
836pub const LT_LINK_READY4 : MTBRegister<'static> = MTBRegister {
837 addr : 0x1e,
838 mask : 0x1ff,
839 descr : "LT link 4 ready",
840 rmw : false,
841 ro : true,
842 pulse : false,
843};
844
845/// LTB Hit counter for slot 0
846//LT0 0x20 0x80 \[23:0\] r hit count on LT=0
847pub const LT0 : MTBRegister<'static> = MTBRegister {
848 addr : 0x20,
849 mask : 0x00ffffff,
850 descr : "Hit count on LT=0",
851 rmw : false,
852 ro : true,
853 pulse : false,
854};
855
856/// LTB Hit counter for slot 1
857//LT1 0x21 0x80 \[23:0\] r hit count on LT=1
858pub const LT1 : MTBRegister<'static> = MTBRegister {
859 addr : 0x21,
860 mask : 0x00ffffff,
861 descr : "Hit count on LT=1",
862 rmw : false,
863 ro : true,
864 pulse : false,
865};
866
867/// LTB Hit counter for slot 2
868//LT2 0x22 0x80 \[23:0\] r hit count on LT=2
869pub const LT2 : MTBRegister<'static> = MTBRegister {
870 addr : 0x22,
871 mask : 0x00ffffff,
872 descr : "Hit count on LT=2",
873 rmw : false,
874 ro : true,
875 pulse : false,
876};
877
878/// LTB Hit counter for slot 3
879//LT3 0x23 0x80 \[23:0\] r hit count on LT=3
880pub const LT3 : MTBRegister<'static> = MTBRegister {
881 addr : 0x23,
882 mask : 0x00ffffff,
883 descr : "Hit count on LT=3",
884 rmw : false,
885 ro : true,
886 pulse : false,
887};
888
889/// LTB Hit counter for slot 4
890//LT4 0x24 0x80 \[23:0\] r hit count on LT=4
891pub const LT4 : MTBRegister<'static> = MTBRegister {
892 addr : 0x24,
893 mask : 0x00ffffff,
894 descr : "Hit count on LT=4",
895 rmw : false,
896 ro : true,
897 pulse : false,
898};
899
900/// LTB Hit counter for slot 5
901//LT5 0x20 0x80 \[23:0\] r hit count on LT=5
902pub const LT5 : MTBRegister<'static> = MTBRegister {
903 addr : 0x25,
904 mask : 0x00ffffff,
905 descr : "Hit count on LT=5",
906 rmw : false,
907 ro : true,
908 pulse : false,
909};
910
911/// LTB Hit counter for slot 6
912/// LT6 0x26 0x80 \[23:0\] r hit count on LT=6
913pub const LT6 : MTBRegister<'static> = MTBRegister {
914 addr : 0x26,
915 mask : 0x00ffffff,
916 descr : "Hit count on LT=6",
917 rmw : false,
918 ro : true,
919 pulse : false,
920};
921
922/// LTB Hit counter for slot 7
923/// LT7 0x27 0x80 \[23:0\] r hit count on LT=7
924pub const LT7 : MTBRegister<'static> = MTBRegister {
925 addr : 0x27,
926 mask : 0x00ffffff,
927 descr : "Hit count on LT=7",
928 rmw : false,
929 ro : true,
930 pulse : false,
931};
932
933
934/// LTB Hit counter for slot 8
935/// LT8 0x28 0x80 \[23:0\] r hit count on LT=8
936pub const LT8 : MTBRegister<'static> = MTBRegister {
937 addr : 0x28,
938 mask : 0x00ffffff,
939 descr : "Hit count on LT=8",
940 rmw : false,
941 ro : true,
942 pulse : false,
943};
944
945
946/// LTB Hit counter for slot 9
947/// LT8 0x29 0x80 \[23:0\] r hit count on LT=9
948pub const LT9 : MTBRegister<'static> = MTBRegister {
949 addr : 0x29,
950 mask : 0x00ffffff,
951 descr : "Hit count on LT=9",
952 rmw : false,
953 ro : true,
954 pulse : false,
955};
956
957
958/// LTB Hit counter for slot 10
959/// LT10 0x2a 0x80 \[23:0\] r hit count on LT=10
960pub const LT10 : MTBRegister<'static> = MTBRegister {
961 addr : 0x2a,
962 mask : 0x00ffffff,
963 descr : "Hit count on LT=10",
964 rmw : false,
965 ro : true,
966 pulse : false,
967};
968
969
970/// LTB Hit counter for slot 11
971/// LT11 0x2b 0x80 \[23:0\] r hit count on LT=11
972pub const LT11 : MTBRegister<'static> = MTBRegister {
973 addr : 0x2b,
974 mask : 0x00ffffff,
975 descr : "Hit count on LT=11",
976 rmw : false,
977 ro : true,
978 pulse : false,
979};
980
981
982/// LTB Hit counter for slot 12
983/// LT12 0x2c 0x80 \[23:0\] r hit count on LT=12
984pub const LT12 : MTBRegister<'static> = MTBRegister {
985 addr : 0x2c,
986 mask : 0x00ffffff,
987 descr : "Hit count on LT=12",
988 rmw : false,
989 ro : true,
990 pulse : false,
991};
992
993/// LTB Hit counter for slot 13
994/// LT13 0x2d 0x80 \[23:0\] r hit count on LT=13
995pub const LT13 : MTBRegister<'static> = MTBRegister {
996 addr : 0x2d,
997 mask : 0x00ffffff,
998 descr : "Hit count on LT=13",
999 rmw : false,
1000 ro : true,
1001 pulse : false,
1002};
1003
1004/// LTB Hit counter for slot 14
1005/// LT14 0x2e 0x80 \[23:0\] r hit count on LT=14
1006pub const LT14 : MTBRegister<'static> = MTBRegister {
1007 addr : 0x2e,
1008 mask : 0x00ffffff,
1009 descr : "Hit count on LT=14",
1010 rmw : false,
1011 ro : true,
1012 pulse : false,
1013};
1014
1015/// LTB Hit counter for slot 15
1016/// LT15 0x2f 0x80 \[23:0\] r hit count on LT=15
1017pub const LT15 : MTBRegister<'static> = MTBRegister {
1018 addr : 0x2f,
1019 mask : 0x00ffffff,
1020 descr : "Hit count on LT=15",
1021 rmw : false,
1022 ro : true,
1023 pulse : false,
1024};
1025
1026/// LTB Hit counter for slot 16
1027/// LT16 0x30 0x80 \[23:0\] r hit count on LT=16
1028pub const LT16 : MTBRegister<'static> = MTBRegister {
1029 addr : 0x30,
1030 mask : 0x00ffffff,
1031 descr : "Hit count on LT=16",
1032 rmw : false,
1033 ro : true,
1034 pulse : false,
1035};
1036
1037/// LTB Hit counter for slot 17
1038/// LT17 0x31 0x80 \[23:0\] r hit count on LT=17
1039pub const LT17 : MTBRegister<'static> = MTBRegister {
1040 addr : 0x31,
1041 mask : 0x00ffffff,
1042 descr : "Hit count on LT=17",
1043 rmw : false,
1044 ro : true,
1045 pulse : false,
1046};
1047
1048/// LTB Hit counter for slot 18
1049/// LT18 0x32 0x80 \[23:0\] r hit count on LT=18
1050pub const LT18 : MTBRegister<'static> = MTBRegister {
1051 addr : 0x32,
1052 mask : 0x00ffffff,
1053 descr : "Hit count on LT=18",
1054 rmw : false,
1055 ro : true,
1056 pulse : false,
1057};
1058
1059/// LTB Hit counter for slot 19
1060/// LT19 0x33 0x80 \[23:0\] r hit count on LT=19
1061pub const LT19 : MTBRegister<'static> = MTBRegister {
1062 addr : 0x33,
1063 mask : 0x00ffffff,
1064 descr : "Hit count on LT=19",
1065 rmw : false,
1066 ro : true,
1067 pulse : false,
1068};
1069
1070
1071/// LTB Hit counter for slot 20
1072/// LT20 0x34 0x80 \[23:0\] r hit count on LT=20
1073pub const LT20 : MTBRegister<'static> = MTBRegister {
1074 addr : 0x34,
1075 mask : 0x00ffffff,
1076 descr : "Hit count on LT=20",
1077 rmw : false,
1078 ro : true,
1079 pulse : false,
1080};
1081
1082/// LTB Hit counter for slot 0
1083/// LT21 0x35 0x80 \[23:0\] r hit count on LT=21
1084pub const LT21 : MTBRegister<'static> = MTBRegister {
1085 addr : 0x35,
1086 mask : 0x00ffffff,
1087 descr : "Hit count on LT=21",
1088 rmw : false,
1089 ro : true,
1090 pulse : false,
1091};
1092
1093/// LTB Hit counter for slot 22
1094/// LT22 0x36 0x80 \[23:0\] r hit count on LT=22
1095pub const LT22 : MTBRegister<'static> = MTBRegister {
1096 addr : 0x36,
1097 mask : 0x00ffffff,
1098 descr : "Hit count on LT=22",
1099 rmw : false,
1100 ro : true,
1101 pulse : false,
1102};
1103
1104/// LTB Hit counter for slot 23
1105/// LT23 0x37 0x80 \[23:0\] r hit count on LT=23
1106pub const LT23 : MTBRegister<'static> = MTBRegister {
1107 addr : 0x37,
1108 mask : 0x00ffffff,
1109 descr : "Hit count on LT=23",
1110 rmw : false,
1111 ro : true,
1112 pulse : false,
1113};
1114
1115/// LTB Hit counter for slot 24
1116/// LT24 0x38 0x80 \[23:0\] r hit count on LT=38
1117pub const LT24 : MTBRegister<'static> = MTBRegister {
1118 addr : 0x38,
1119 mask : 0x00ffffff,
1120 descr : "Hit count on LT=24",
1121 rmw : false,
1122 ro : true,
1123 pulse : false,
1124};
1125
1126/// LTB Hit counter reset
1127/// RESET 0x39 0xe4 0 w Pulse Write 1 to reset hit counters.
1128pub const LT_HIT_CNT_RESET : MTBRegister<'static> = MTBRegister {
1129 addr : 0x39,
1130 mask : 0x00000001,
1131 descr : "Reset LT HIT counters 0-24",
1132 rmw : false,
1133 ro : false,
1134 pulse : true,
1135};
1136
1137/// LTB Hit counter snap
1138/// SNAP 0x3a 0xe8 0 rw 0x1 1 to snap the hit counters.
1139pub const LT_HIT_CNT_SNAP : MTBRegister<'static> = MTBRegister {
1140 addr : 0x3a,
1141 mask : 0x00000001,
1142 descr : "Snap LT HIT counters 0-24",
1143 rmw : true,
1144 ro : false,
1145 pulse : false,
1146};
1147
1148/// LTB channel mask, set 1 to a channel to mask (deactivate it)
1149///
1150/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1151/// one bit per channel
1152/// LT0 0x50 0x140 \[7:0\] rw 0x0 1 to mask a channel of LT=0
1153pub const LT0_CHMASK : MTBRegister<'static> = MTBRegister {
1154 addr : 0x50,
1155 mask : 0x000000f,
1156 descr : "Channel mask for LT=0",
1157 rmw : true,
1158 ro : false,
1159 pulse : false,
1160};
1161
1162/// LT1 channel mask, set 1 to a channel to mask (deactivate it)
1163///
1164/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1165/// one bit per channel
1166/// LT1 0x51 0x144 \[7:0\] rw 0x0 1 to mask a channel of LT=1
1167pub const LT1_CHMASK : MTBRegister<'static> = MTBRegister {
1168 addr : 0x51,
1169 mask : 0x000000f,
1170 descr : "Channel mask for LT=1",
1171 rmw : true,
1172 ro : false,
1173 pulse : false,
1174};
1175
1176/// LT2 channel mask, set 1 to a channel to mask (deactivate it)
1177///
1178/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1179/// one bit per channel
1180/// LT2 0x52 0x148 \[7:0\] rw 0x0 1 to mask a channel of LT=2
1181pub const LT2_CHMASK : MTBRegister<'static> = MTBRegister {
1182 addr : 0x52,
1183 mask : 0x000000f,
1184 descr : "Channel mask for LT=2",
1185 rmw : true,
1186 ro : false,
1187 pulse : false,
1188};
1189
1190/// LT3 channel mask, set 1 to a channel to mask (deactivate it)
1191///
1192/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1193/// one bit per channel
1194/// LT3 0x53 0x14c \[7:0\] rw 0x0 1 to mask a channel of LT=3
1195pub const LT3_CHMASK : MTBRegister<'static> = MTBRegister {
1196 addr : 0x53,
1197 mask : 0x000000f,
1198 descr : "Channel mask for LT=3",
1199 rmw : true,
1200 ro : false,
1201 pulse : false,
1202};
1203
1204/// LT4 channel mask, set 1 to a channel to mask (deactivate it)
1205///
1206/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1207/// one bit per channel
1208/// LT4 0x54 0x150 \[7:0\] rw 0x0 1 to mask a channel of LT=4
1209pub const LT4_CHMASK : MTBRegister<'static> = MTBRegister {
1210 addr : 0x54,
1211 mask : 0x000000f,
1212 descr : "Channel mask for LT=4",
1213 rmw : true,
1214 ro : false,
1215 pulse : false,
1216};
1217
1218/// LT5 channel mask, set 1 to a channel to mask (deactivate it)
1219///
1220/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1221/// one bit per channel
1222/// LT5 0x55 0x154 \[7:0\] rw 0x0 1 to mask a channel of LT=5
1223pub const LT5_CHMASK : MTBRegister<'static> = MTBRegister {
1224 addr : 0x55,
1225 mask : 0x000000f,
1226 descr : "Channel mask for LT=5",
1227 rmw : true,
1228 ro : false,
1229 pulse : false,
1230};
1231
1232/// LT6 channel mask, set 1 to a channel to mask (deactivate it)
1233///
1234/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1235/// one bit per channel
1236/// LT6 0x56 0x158 \[7:0\] rw 0x0 1 to mask a channel of LT=6
1237pub const LT6_CHMASK : MTBRegister<'static> = MTBRegister {
1238 addr : 0x56,
1239 mask : 0x000000f,
1240 descr : "Channel mask for LT=6",
1241 rmw : true,
1242 ro : false,
1243 pulse : false,
1244};
1245
1246/// LT7 channel mask, set 1 to a channel to mask (deactivate it)
1247///
1248/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1249/// one bit per channel
1250/// LT7 0x57 0x15c \[7:0\] rw 0x0 1 to mask a channel of LT=7
1251pub const LT7_CHMASK : MTBRegister<'static> = MTBRegister {
1252 addr : 0x57,
1253 mask : 0x000000f,
1254 descr : "Channel mask for LT=7",
1255 rmw : true,
1256 ro : false,
1257 pulse : false,
1258};
1259
1260/// LT8 channel mask, set 1 to a channel to mask (deactivate it)
1261///
1262/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1263/// one bit per channel
1264/// LT8 0x58 0x160 \[7:0\] rw 0x0 1 to mask a channel of LT=8
1265pub const LT8_CHMASK : MTBRegister<'static> = MTBRegister {
1266 addr : 0x58,
1267 mask : 0x000000f,
1268 descr : "Channel mask for LT=8",
1269 rmw : true,
1270 ro : false,
1271 pulse : false,
1272};
1273
1274/// LT9 channel mask, set 1 to a channel to mask (deactivate it)
1275///
1276/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1277/// one bit per channel
1278/// LT9 0x59 0x164 \[7:0\] rw 0x0 1 to mask a channel of LT=9
1279pub const LT9_CHMASK : MTBRegister<'static> = MTBRegister {
1280 addr : 0x59,
1281 mask : 0x000000f,
1282 descr : "Channel mask for LT=9",
1283 rmw : true,
1284 ro : false,
1285 pulse : false,
1286};
1287
1288/// LT10 channel mask, set 1 to a channel to mask (deactivate it)
1289///
1290/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1291/// one bit per channel
1292/// LT10 0x5a 0x168 \[7:0\] rw 0x0 1 to mask a channel of LT=10
1293pub const LT10_CHMASK : MTBRegister<'static> = MTBRegister {
1294 addr : 0x5a,
1295 mask : 0x000000f,
1296 descr : "Channel mask for LT=10",
1297 rmw : true,
1298 ro : false,
1299 pulse : false,
1300};
1301
1302/// LT11 channel mask, set 1 to a channel to mask (deactivate it)
1303///
1304/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1305/// one bit per channel
1306/// LT11 0x5b 0x16c \[7:0\] rw 0x0 1 to mask a channel of LT=11
1307pub const LT11_CHMASK : MTBRegister<'static> = MTBRegister {
1308 addr : 0x5b,
1309 mask : 0x000000f,
1310 descr : "Channel mask for LT=11",
1311 rmw : true,
1312 ro : false,
1313 pulse : false,
1314};
1315
1316/// LT12 channel mask, set 1 to a channel to mask (deactivate it)
1317///
1318/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1319/// one bit per channel
1320/// LT12 0x5c 0x170 \[7:0\] rw 0x0 1 to mask a channel of LT=12
1321pub const LT12_CHMASK : MTBRegister<'static> = MTBRegister {
1322 addr : 0x5c,
1323 mask : 0x000000f,
1324 descr : "Channel mask for LT=12",
1325 rmw : true,
1326 ro : false,
1327 pulse : false,
1328};
1329
1330/// LT13 channel mask, set 1 to a channel to mask (deactivate it)
1331///
1332/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1333/// one bit per channel
1334/// LT13 0x5d 0x174 \[7:0\] rw 0x0 1 to mask a channel of LT=13
1335pub const LT13_CHMASK : MTBRegister<'static> = MTBRegister {
1336 addr : 0x5d,
1337 mask : 0x000000f,
1338 descr : "Channel mask for LT=13",
1339 rmw : true,
1340 ro : false,
1341 pulse : false,
1342};
1343
1344/// LT14 channel mask, set 1 to a channel to mask (deactivate it)
1345///
1346/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1347/// one bit per channel
1348/// LT14 0x5e 0x178 \[7:0\] rw 0x0 1 to mask a channel of LT=14
1349pub const LT14_CHMASK : MTBRegister<'static> = MTBRegister {
1350 addr : 0x5e,
1351 mask : 0x000000f,
1352 descr : "Channel mask for LT=14",
1353 rmw : true,
1354 ro : false,
1355 pulse : false,
1356};
1357
1358/// LT15 channel mask, set 1 to a channel to mask (deactivate it)
1359///
1360/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1361/// one bit per channel
1362/// LT15 0x5f 0x17c \[7:0\] rw 0x0 1 to mask a channel of LT=15
1363pub const LT15_CHMASK : MTBRegister<'static> = MTBRegister {
1364 addr : 0x5f,
1365 mask : 0x000000f,
1366 descr : "Channel mask for LT=15",
1367 rmw : true,
1368 ro : false,
1369 pulse : false,
1370};
1371
1372/// LT16 channel mask, set 1 to a channel to mask (deactivate it)
1373///
1374/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1375/// one bit per channel
1376/// LT16 0x60 0x180 \[7:0\] rw 0x0 1 to mask a channel of LT=16
1377pub const LT16_CHMASK : MTBRegister<'static> = MTBRegister {
1378 addr : 0x60,
1379 mask : 0x000000f,
1380 descr : "Channel mask for LT=16",
1381 rmw : true,
1382 ro : false,
1383 pulse : false,
1384};
1385
1386/// LT17 channel mask, set 1 to a channel to mask (deactivate it)
1387///
1388/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1389/// one bit per channel
1390/// LT17 0x61 0x184 \[7:0\] rw 0x0 1 to mask a channel of LT=17
1391pub const LT17_CHMASK : MTBRegister<'static> = MTBRegister {
1392 addr : 0x61,
1393 mask : 0x000000f,
1394 descr : "Channel mask for LT=17",
1395 rmw : true,
1396 ro : false,
1397 pulse : false,
1398};
1399
1400/// LT18 channel mask, set 1 to a channel to mask (deactivate it)
1401///
1402/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1403/// one bit per channel
1404/// LT18 0x62 0x188 \[7:0\] rw 0x0 1 to mask a channel of LT=18
1405pub const LT18_CHMASK : MTBRegister<'static> = MTBRegister {
1406 addr : 0x62,
1407 mask : 0x000000f,
1408 descr : "Channel mask for LT=18",
1409 rmw : true,
1410 ro : false,
1411 pulse : false,
1412};
1413
1414/// LT19 channel mask, set 1 to a channel to mask (deactivate it)
1415///
1416/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1417/// one bit per channel
1418/// LT19 0x63 0x18c \[7:0\] rw 0x0 1 to mask a channel of LT=19
1419pub const LT19_CHMASK : MTBRegister<'static> = MTBRegister {
1420 addr : 0x63,
1421 mask : 0x000000f,
1422 descr : "Channel mask for LT=19",
1423 rmw : true,
1424 ro : false,
1425 pulse : false,
1426};
1427
1428/// LT20 channel mask, set 1 to a channel to mask (deactivate it)
1429///
1430/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1431/// one bit per channel
1432/// LT20 0x64 0x190 \[7:0\] rw 0x0 1 to mask a channel of LT=20
1433pub const LT20_CHMASK : MTBRegister<'static> = MTBRegister {
1434 addr : 0x64,
1435 mask : 0x000000f,
1436 descr : "Channel mask for LT=20",
1437 rmw : true,
1438 ro : false,
1439 pulse : false,
1440};
1441
1442/// LT21 channel mask, set 1 to a channel to mask (deactivate it)
1443///
1444/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1445/// one bit per channel
1446/// LT21 0x65 0x194 \[7:0\] rw 0x0 1 to mask a channel of LT=21
1447pub const LT21_CHMASK : MTBRegister<'static> = MTBRegister {
1448 addr : 0x65,
1449 mask : 0x000000f,
1450 descr : "Channel mask for LT=21",
1451 rmw : true,
1452 ro : false,
1453 pulse : false,
1454};
1455
1456/// LT22 channel mask, set 1 to a channel to mask (deactivate it)
1457///
1458/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1459/// one bit per channel
1460/// LT22 0x66 0x198 \[7:0\] rw 0x0 1 to mask a channel of LT=22
1461pub const LT22_CHMASK : MTBRegister<'static> = MTBRegister {
1462 addr : 0x66,
1463 mask : 0x000000f,
1464 descr : "Channel mask for LT=22",
1465 rmw : true,
1466 ro : false,
1467 pulse : false,
1468};
1469
1470/// LT23 channel mask, set 1 to a channel to mask (deactivate it)
1471///
1472/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1473/// one bit per channel
1474/// LT23 0x67 0x19c \[7:0\] rw 0x0 1 to mask a channel of LT=23
1475pub const LT23_CHMASK : MTBRegister<'static> = MTBRegister {
1476 addr : 0x67,
1477 mask : 0x000000f,
1478 descr : "Channel mask for LT=23",
1479 rmw : true,
1480 ro : false,
1481 pulse : false,
1482};
1483
1484/// LT24 channel mask, set 1 to a channel to mask (deactivate it)
1485///
1486/// Sets the mask for all channels 0-7 for this LTB simultaneously,
1487/// one bit per channel
1488/// LT24 0x68 0x1a0 \[7:0\] rw 0x0 1 to mask a channel of LT=24
1489pub const LT24_CHMASK : MTBRegister<'static> = MTBRegister {
1490 addr : 0x68,
1491 mask : 0x000000f,
1492 descr : "Channel mask for LT=24",
1493 rmw : true,
1494 ro : false,
1495 pulse : false,
1496};
1497
1498
1499//MT.RB_READOUT_CNTS
1500//
1501//Counters
1502
1503/// Readout counter on RB=0
1504/// CNTS_0 0xf2 0x3c8 \[7:0\] r Readout count on RB=0
1505pub const RB0_CNTS : MTBRegister<'static> = MTBRegister {
1506 addr : 0xf2,
1507 mask : 0x000000ff,
1508 descr : "Counts on RB0/(link id?)",
1509 rmw : false,
1510 ro : true,
1511 pulse : false,
1512};
1513
1514/// Readout counter on RB=1
1515/// CNTS_1 0xf2 0x3c8 \[15:8\] r Readout count on RB=1
1516pub const RB1_CNTS : MTBRegister<'static> = MTBRegister {
1517 addr : 0xf2,
1518 mask : 0x0000ff00,
1519 descr : "Counts on RB1/(link id?)",
1520 rmw : false,
1521 ro : true,
1522 pulse : false,
1523};
1524
1525/// Readout counter on RB=2
1526/// CNTS_2 0xf2 0x3c8 \[23:16\] r Readout count on RB=2
1527pub const RB2_CNTS : MTBRegister<'static> = MTBRegister {
1528 addr : 0xf2,
1529 mask : 0x00ff0000,
1530 descr : "Counts on RB2/(link id?)",
1531 rmw : false,
1532 ro : true,
1533 pulse : false,
1534};
1535
1536/// Readout counter on RB=3
1537/// CNTS_3 0xf2 0x3c8 \[31:24\] r Readout count on RB=3
1538pub const RB3_CNTS : MTBRegister<'static> = MTBRegister {
1539 addr : 0xf2,
1540 mask : 0xff000000,
1541 descr : "Counts on RB3/(link id?)",
1542 rmw : false,
1543 ro : true,
1544 pulse : false,
1545};
1546
1547/// Readout counter on RB=4
1548/// CNTS_4 0xf3 0x3cc \[7:0\] r Readout count on RB=4
1549pub const RB4_CNTS : MTBRegister<'static> = MTBRegister {
1550 addr : 0xf3,
1551 mask : 0x000000ff,
1552 descr : "Counts on RB4/(link id?)",
1553 rmw : false,
1554 ro : true,
1555 pulse : false,
1556};
1557
1558/// Readout counter on RB=5
1559/// CNTS_5 0xf3 0x3cc \[15:8\] r Readout count on RB=5
1560pub const RB5_CNTS : MTBRegister<'static> = MTBRegister {
1561 addr : 0xf3,
1562 mask : 0x0000ff00,
1563 descr : "Counts on RB5/(link id?)",
1564 rmw : false,
1565 ro : true,
1566 pulse : false,
1567};
1568
1569/// Readout counter on RB=6
1570/// CNTS_6 0xf3 0x3cc \[23:16\] r Readout count on RB=6
1571pub const RB6_CNTS : MTBRegister<'static> = MTBRegister {
1572 addr : 0xf3,
1573 mask : 0x00ff0000,
1574 descr : "Counts on RB6/(link id?)",
1575 rmw : false,
1576 ro : true,
1577 pulse : false,
1578};
1579
1580/// Readout counter on RB=7
1581/// CNTS_7 0xf3 0x3cc \[31:24\] r Readout count on RB=7
1582pub const RB7_CNTS : MTBRegister<'static> = MTBRegister {
1583 addr : 0xf3,
1584 mask : 0xff000000,
1585 descr : "Counts on RB7/(link id?)",
1586 rmw : false,
1587 ro : true,
1588 pulse : false,
1589};
1590
1591/// Readout counter on RB=8
1592/// CNTS_8 0xf4 0x3d0 \[7:0\] r Readout count on RB=8
1593pub const RB8_CNTS : MTBRegister<'static> = MTBRegister {
1594 addr : 0xf4,
1595 mask : 0x000000ff,
1596 descr : "Counts on RB8/(link id?)",
1597 rmw : false,
1598 ro : true,
1599 pulse : false,
1600};
1601
1602/// Readout counter on RB=9
1603/// CNTS_9 0xf4 0x3d0 \[15:8\] r Readout count on RB=9
1604pub const RB9_CNTS : MTBRegister<'static> = MTBRegister {
1605 addr : 0xf4,
1606 mask : 0x0000ff00,
1607 descr : "Counts on RB9/(link id?)",
1608 rmw : false,
1609 ro : true,
1610 pulse : false,
1611};
1612
1613/// Readout counter on RB=10
1614/// CNTS_10 0xf4 0x3d0 \[23:16\] r Readout count on RB=10
1615pub const RB10_CNTS : MTBRegister<'static> = MTBRegister {
1616 addr : 0xf4,
1617 mask : 0x00ff0000,
1618 descr : "Counts on RB10/(link id?)",
1619 rmw : false,
1620 ro : true,
1621 pulse : false,
1622};
1623
1624/// Readout counter on RB=11
1625/// CNTS_11 0xf4 0x3d0 \[31:24\] r Readout count on RB=11
1626pub const RB11_CNTS : MTBRegister<'static> = MTBRegister {
1627 addr : 0xf4,
1628 mask : 0xff000000,
1629 descr : "Counts on RB11/(link id?)",
1630 rmw : false,
1631 ro : true,
1632 pulse : false,
1633};
1634
1635/// Readout counter on RB=12
1636/// CNTS_12 0xf5 0x3d4 \[7:0\] r Readout count on RB=12
1637pub const RB12_CNTS : MTBRegister<'static> = MTBRegister {
1638 addr : 0xf5,
1639 mask : 0x000000ff,
1640 descr : "Counts on RB12/(link id?)",
1641 rmw : false,
1642 ro : true,
1643 pulse : false,
1644};
1645
1646/// Readout counter on RB=13
1647/// CNTS_13 0xf5 0x3d4 \[15:8\] r Readout count on RB=13
1648pub const RB13_CNTS : MTBRegister<'static> = MTBRegister {
1649 addr : 0xf5,
1650 mask : 0x0000ff00,
1651 descr : "Counts on RB13/(link id?)",
1652 rmw : false,
1653 ro : true,
1654 pulse : false,
1655};
1656
1657/// Readout counter on RB=14
1658/// CNTS_14 0xf5 0x3d4 \[23:16\] r Readout count on RB=14
1659pub const RB14_CNTS : MTBRegister<'static> = MTBRegister {
1660 addr : 0xf5,
1661 mask : 0x00ff0000,
1662 descr : "Counts on RB14/(link id?)",
1663 rmw : false,
1664 ro : true,
1665 pulse : false,
1666};
1667
1668/// Readout counter on RB=15
1669/// CNTS_15 0xf5 0x3d4 \[31:24\] r Readout count on RB=15
1670pub const RB15_CNTS : MTBRegister<'static> = MTBRegister {
1671 addr : 0xf5,
1672 mask : 0xff000000,
1673 descr : "Counts on RB15/(link id?)",
1674 rmw : false,
1675 ro : true,
1676 pulse : false,
1677};
1678
1679/// Readout counter on RB=16
1680/// CNTS_16 0xf6 0x3d8 \[7:0\] r Readout count on RB=16
1681pub const RB16_CNTS : MTBRegister<'static> = MTBRegister {
1682 addr : 0xf6,
1683 mask : 0x000000ff,
1684 descr : "Counts on RB16/(link id?)",
1685 rmw : false,
1686 ro : true,
1687 pulse : false,
1688};
1689
1690/// Readout counter on RB=17
1691/// CNTS_17 0xf6 0x3d8 \[15:8\] r Readout count on RB=17
1692pub const RB17_CNTS : MTBRegister<'static> = MTBRegister {
1693 addr : 0xf6,
1694 mask : 0x0000ff00,
1695 descr : "Counts on RB14/(link id?)",
1696 rmw : false,
1697 ro : true,
1698 pulse : false,
1699};
1700
1701/// Readout counter on RB=18
1702/// CNTS_18 0xf6 0x3d8 \[23:16\] r Readout count on RB=18
1703pub const RB18_CNTS : MTBRegister<'static> = MTBRegister {
1704 addr : 0xf6,
1705 mask : 0x00ff0000,
1706 descr : "Counts on RB18/(link id?)",
1707 rmw : false,
1708 ro : true,
1709 pulse : false,
1710};
1711
1712/// Readout counter on RB=19
1713/// CNTS_19 0xf6 0x3d8 \[31:24\] r Readout count on RB=19
1714pub const RB19_CNTS : MTBRegister<'static> = MTBRegister {
1715 addr : 0xf6,
1716 mask : 0xff000000,
1717 descr : "Counts on RB19/(link id?)",
1718 rmw : false,
1719 ro : true,
1720 pulse : false,
1721};
1722
1723/// Readout counter on RB=20
1724/// CNTS_20 0xf7 0x3dc \[7:0\] r Readout count on RB=20
1725pub const RB20_CNTS : MTBRegister<'static> = MTBRegister {
1726 addr : 0xf7,
1727 mask : 0x000000ff,
1728 descr : "Counts on RB20/(link id?)",
1729 rmw : false,
1730 ro : true,
1731 pulse : false,
1732};
1733
1734/// Readout counter on RB=21
1735/// CNTS_21 0xf7 0x3dc \[15:8\] r Readout count on RB=21
1736pub const RB21_CNTS : MTBRegister<'static> = MTBRegister {
1737 addr : 0xf7,
1738 mask : 0x0000ff00,
1739 descr : "Counts on RB21/(link id?)",
1740 rmw : false,
1741 ro : true,
1742 pulse : false,
1743};
1744
1745/// Readout counter on RB=22
1746/// CNTS_22 0xf7 0x3dc \[23:16\] r Readout count on RB=22
1747pub const RB22_CNTS : MTBRegister<'static> = MTBRegister {
1748 addr : 0xf7,
1749 mask : 0x00ff0000,
1750 descr : "Counts on RB22/(link id?)",
1751 rmw : false,
1752 ro : true,
1753 pulse : false,
1754};
1755
1756/// Readout counter on RB=23
1757/// CNTS_23 0xf7 0x3dc \[31:24\] r Readout count on RB=23
1758pub const RB23_CNTS : MTBRegister<'static> = MTBRegister {
1759 addr : 0xf7,
1760 mask : 0xff000000,
1761 descr : "Counts on RB23/(link id?)",
1762 rmw : false,
1763 ro : true,
1764 pulse : false,
1765};
1766
1767/// Readout counter on RB=24
1768/// CNTS_24 0xf8 0x3e0 \[7:0\] r Readout count on RB=24
1769pub const RB24_CNTS : MTBRegister<'static> = MTBRegister {
1770 addr : 0xf8,
1771 mask : 0x000000ff,
1772 descr : "Counts on RB24/(link id?)",
1773 rmw : false,
1774 ro : true,
1775 pulse : false,
1776};
1777
1778/// Readout counter on RB=25
1779/// CNTS_25 0xf8 0x3e0 \[15:8\] r Readout count on RB=25
1780pub const RB25_CNTS : MTBRegister<'static> = MTBRegister {
1781 addr : 0xf8,
1782 mask : 0x0000ff00,
1783 descr : "Counts on RB25/(link id?)",
1784 rmw : false,
1785 ro : true,
1786 pulse : false,
1787};
1788
1789/// Readout counter on RB=26
1790/// CNTS_26 0xf8 0x3e0 \[23:16\] r Readout count on RB=26
1791pub const RB26_CNTS : MTBRegister<'static> = MTBRegister {
1792 addr : 0xf8,
1793 mask : 0x00ff0000,
1794 descr : "Counts on RB26/(link id?)",
1795 rmw : false,
1796 ro : true,
1797 pulse : false,
1798};
1799
1800/// Readout counter on RB=27
1801/// CNTS_27 0xf8 0x3e0 \[31:24\] r Readout count on RB=27
1802pub const RB27_CNTS : MTBRegister<'static> = MTBRegister {
1803 addr : 0xf8,
1804 mask : 0xff000000,
1805 descr : "Counts on RB27/(link id?)",
1806 rmw : false,
1807 ro : true,
1808 pulse : false,
1809};
1810
1811/// Readout counter on RB=28
1812/// CNTS_28 0xf9 0x3e4 \[7:0\] r Readout count on RB=28
1813pub const RB28_CNTS : MTBRegister<'static> = MTBRegister {
1814 addr : 0xf9,
1815 mask : 0x000000ff,
1816 descr : "Counts on RB28/(link id?)",
1817 rmw : false,
1818 ro : true,
1819 pulse : false,
1820};
1821
1822/// Readout counter on RB=29
1823/// CNTS_29 0xf9 0x3e4 \[15:8\] r Readout count on RB=29
1824pub const RB29_CNTS : MTBRegister<'static> = MTBRegister {
1825 addr : 0xf9,
1826 mask : 0x0000ff00,
1827 descr : "Counts on RB29/(link id?)",
1828 rmw : false,
1829 ro : true,
1830 pulse : false,
1831};
1832
1833/// Readout counter on RB=30
1834/// CNTS_30 0xf9 0x3e4 \[23:16\] r Readout count on RB=30
1835pub const RB30_CNTS : MTBRegister<'static> = MTBRegister {
1836 addr : 0xf9,
1837 mask : 0x00ff0000,
1838 descr : "Counts on RB30/(link id?)",
1839 rmw : false,
1840 ro : true,
1841 pulse : false,
1842};
1843
1844/// Readout counter on RB=31
1845/// CNTS_31 0xf9 0x3e4 \[31:24\] r Readout count on RB=31
1846pub const RB31_CNTS : MTBRegister<'static> = MTBRegister {
1847 addr : 0xf9,
1848 mask : 0xff000000,
1849 descr : "Counts on RB31/(link id?)",
1850 rmw : false,
1851 ro : true,
1852 pulse : false,
1853};
1854
1855/// Readout counter on RB=32
1856/// CNTS_32 0xfa 0x3e8 \[7:0\] r Readout count on RB=32
1857pub const RB32_CNTS : MTBRegister<'static> = MTBRegister {
1858 addr : 0xfa,
1859 mask : 0x000000ff,
1860 descr : "Counts on RB32/(link id?)",
1861 rmw : false,
1862 ro : true,
1863 pulse : false,
1864};
1865
1866/// Readout counter on RB=33
1867/// CNTS_33 0xfa 0x3e8 \[15:8\] r Readout count on RB=33
1868pub const RB33_CNTS : MTBRegister<'static> = MTBRegister {
1869 addr : 0xfa,
1870 mask : 0x0000ff00,
1871 descr : "Counts on RB33/(link id?)",
1872 rmw : false,
1873 ro : true,
1874 pulse : false,
1875};
1876
1877/// Readout counter on RB=34
1878/// CNTS_34 0xfa 0x3e8 \[23:16\] r Readout count on RB=34
1879pub const RB34_CNTS : MTBRegister<'static> = MTBRegister {
1880 addr : 0xfa,
1881 mask : 0x00ff0000,
1882 descr : "Counts on RB34/(link id?)",
1883 rmw : false,
1884 ro : true,
1885 pulse : false,
1886};
1887
1888/// Readout counter on RB=35
1889/// CNTS_35 0xfa 0x3e8 \[31:24\] r Readout count on RB=35
1890pub const RB35_CNTS : MTBRegister<'static> = MTBRegister {
1891 addr : 0xfa,
1892 mask : 0xff000000,
1893 descr : "Counts on RB35/(link id?)",
1894 rmw : false,
1895 ro : true,
1896 pulse : false,
1897};
1898
1899/// Readout counter on RB=36
1900/// CNTS_36 0xfb 0x3ec \[7:0\] r Readout count on RB=36
1901pub const RB36_CNTS : MTBRegister<'static> = MTBRegister {
1902 addr : 0xfb,
1903 mask : 0x000000ff,
1904 descr : "Counts on RB36/(link id?)",
1905 rmw : false,
1906 ro : true,
1907 pulse : false,
1908};
1909
1910/// Readout counter on RB=37
1911/// CNTS_37 0xfb 0x3ec \[15:8\] r Readout count on RB=37
1912pub const RB37_CNTS : MTBRegister<'static> = MTBRegister {
1913 addr : 0xfb,
1914 mask : 0x0000ff00,
1915 descr : "Counts on RB37/(link id?)",
1916 rmw : false,
1917 ro : true,
1918 pulse : false,
1919};
1920
1921/// Readout counter on RB=38
1922/// CNTS_38 0xfb 0x3ec \[23:16\] r Readout count on RB=38
1923pub const RB38_CNTS : MTBRegister<'static> = MTBRegister {
1924 addr : 0xfb,
1925 mask : 0x00ff0000,
1926 descr : "Counts on RB38/(link id?)",
1927 rmw : false,
1928 ro : true,
1929 pulse : false,
1930};
1931
1932/// Readout counter on RB=39
1933/// CNTS_39 0xfb 0x3ec \[31:24\] r Readout count on RB=39
1934pub const RB39_CNTS : MTBRegister<'static> = MTBRegister {
1935 addr : 0xfb,
1936 mask : 0xff000000,
1937 descr : "Counts on RB39/(link id?)",
1938 rmw : false,
1939 ro : true,
1940 pulse : false,
1941};
1942
1943/// Readout counter on RB=40
1944/// CNTS_40 0xfc 0x3f0 \[7:0\] r Readout count on RB=40
1945pub const RB40_CNTS : MTBRegister<'static> = MTBRegister {
1946 addr : 0xfc,
1947 mask : 0x000000ff,
1948 descr : "Counts on RB40/(link id?)",
1949 rmw : false,
1950 ro : true,
1951 pulse : false,
1952};
1953
1954/// Readout counter on RB=41
1955/// CNTS_41 0xfc 0x3f0 \[15:8\] r Readout count on RB=41
1956pub const RB41_CNTS : MTBRegister<'static> = MTBRegister {
1957 addr : 0xfc,
1958 mask : 0x0000ff00,
1959 descr : "Counts on RB41/(link id?)",
1960 rmw : false,
1961 ro : true,
1962 pulse : false,
1963};
1964
1965/// Readout counter on RB=42
1966/// CNTS_42 0xfc 0x3f0 \[23:16\] r Readout count on RB=42
1967pub const RB42_CNTS : MTBRegister<'static> = MTBRegister {
1968 addr : 0xfc,
1969 mask : 0x00ff0000,
1970 descr : "Counts on RB42/(link id?)",
1971 rmw : false,
1972 ro : true,
1973 pulse : false,
1974};
1975
1976/// Readout counter on RB=43
1977/// CNTS_43 0xfc 0x3f0 \[31:24\] r Readout count on RB=43
1978pub const RB43_CNTS : MTBRegister<'static> = MTBRegister {
1979 addr : 0xfc,
1980 mask : 0xff000000,
1981 descr : "Counts on RB43/(link id?)",
1982 rmw : false,
1983 ro : true,
1984 pulse : false,
1985};
1986
1987/// Readout counter on RB=44
1988/// CNTS_44 0xfd 0x3f4 \[7:0\] r Readout count on RB=44
1989pub const RB44_CNTS : MTBRegister<'static> = MTBRegister {
1990 addr : 0xfd,
1991 mask : 0x000000ff,
1992 descr : "Counts on RB44/(link id?)",
1993 rmw : false,
1994 ro : true,
1995 pulse : false,
1996};
1997
1998/// Readout counter on RB=45
1999/// CNTS_45 0xfd 0x3f4 \[15:8\] r Readout count on RB=45
2000pub const RB45_CNTS : MTBRegister<'static> = MTBRegister {
2001 addr : 0xfd,
2002 mask : 0x0000ff00,
2003 descr : "Counts on RB45/(link id?)",
2004 rmw : false,
2005 ro : true,
2006 pulse : false,
2007};
2008
2009/// Readout counter on RB=46
2010/// CNTS_46 0xfd 0x3f4 \[23:16\] r Readout count on RB=46
2011pub const RB46_CNTS : MTBRegister<'static> = MTBRegister {
2012 addr : 0xfd,
2013 mask : 0x00ff0000,
2014 descr : "Counts on RB46/(link id?)",
2015 rmw : false,
2016 ro : true,
2017 pulse : false,
2018};
2019
2020
2021/// Readout counter on RB=47
2022/// CNTS_47 0xfd 0x3f4 \[31:24\] r Readout count on RB=47
2023pub const RB47_CNTS : MTBRegister<'static> = MTBRegister {
2024 addr : 0xfd,
2025 mask : 0xff000000,
2026 descr : "Counts on RB47/(link id?)",
2027 rmw : false,
2028 ro : true,
2029 pulse : false,
2030};
2031
2032
2033/// Readout counter on RB=48
2034/// CNTS_48 0xfe 0x3f8 \[7:0\] r Readout count on RB=48
2035pub const RB48_CNTS : MTBRegister<'static> = MTBRegister {
2036 addr : 0xfe,
2037 mask : 0x000000ff,
2038 descr : "Counts on RB48/(link id?)",
2039 rmw : false,
2040 ro : true,
2041 pulse : false,
2042};
2043
2044/// Readout counter on RB=49
2045/// CNTS_49 0xfe 0x3f8 \[15:8\] r Readout count on RB=49
2046pub const RB49_CNTS : MTBRegister<'static> = MTBRegister {
2047 addr : 0xfe,
2048 mask : 0x0000ff00,
2049 descr : "Counts on RB49/(link id?)",
2050 rmw : false,
2051 ro : true,
2052 pulse : false,
2053};
2054
2055/// Reset RB counters 0-49
2056/// RESET 0xff 0x3fc 0 w Pulse Write 1 to reset hit counters.
2057pub const RB_CNTS_RESET : MTBRegister<'static> = MTBRegister {
2058 addr : 0xff,
2059 mask : 0x00000001,
2060 descr : "Reset RB counters 1-49",
2061 rmw : false,
2062 ro : false,
2063 pulse : true,
2064};
2065
2066/// Snap RB counters 0-49
2067/// SNAP 0x100 0x400 0 rw 0x1 1 to snap the hit counters.
2068pub const RB_CNTS_SNAP : MTBRegister<'static> = MTBRegister {
2069 addr : 0x100,
2070 mask : 0x00000001,
2071 descr : "Snap RB counters 1-49",
2072 rmw : true,
2073 ro : false,
2074 pulse : false,
2075};
2076
2077/// Add the central track trigger to all triggers
2078/// TRACK_CENTRAL_IS_GLOBAL 0xb 0x2c 2 rw 0x0 1 makes the TRACK central read all paddles.
2079pub const TRACK_CENTRAL_IS_GLOBAL : MTBRegister<'static> = MTBRegister {
2080 addr : 0xb,
2081 mask : 0x4,
2082 descr : "1 makes the TRACK central read all paddles",
2083 rmw : true,
2084 ro : false,
2085 pulse : false,
2086};
2087
2088/// Add the umbrella central track trigger to all triggers
2089/// TRACK_UMB_CENTRAL_IS_GLOBAL 0xb 0x2c 3 rw 0x0 1 makes the TRACK UMB central read all paddles.
2090pub const TRACK_UMB_CENTRAL_IS_GLOBAL : MTBRegister<'static> = MTBRegister {
2091 addr : 0xb,
2092 mask : 0x8,
2093 descr : "1 makes the TRACK UMB CENTRAL trigger read all paddles",
2094 rmw : true,
2095 ro : false,
2096 pulse : false,
2097};
2098
2099/// Add the track trigger to all triggers
2100/// TRACE_TRIG_IS_GLOBAL 0xb 0x2c 1 rw 0x0
2101pub const TRACK_TRIG_IS_GLOBAL : MTBRegister<'static> = MTBRegister {
2102 addr : 0xb,
2103 mask : 0x2,
2104 descr : "1 makes the TRACK trigger read all paddles",
2105 rmw : true,
2106 ro : false,
2107 pulse : false,
2108};
2109
2110/// Add any trigger to all triggers
2111/// ANY_TRIG_IS_GLOBAL 0xb 0x2c 0 rw 0x0
2112pub const ANY_TRIG_IS_GLOBAL : MTBRegister<'static> = MTBRegister {
2113 addr : 0xb,
2114 mask : 0x1,
2115 descr : "1 makes the ANY trigger read all paddles",
2116 rmw : true,
2117 ro : false,
2118 pulse : false,
2119};
2120
2121/// Choose between the 2 different TIU links
2122/// 1 for J11, 0 for J3
2123/// 0xe 0x38 1 rw 0x0 1 to use J11; 0 to use J3
2124pub const TIU_USE_AUX_LINK : MTBRegister<'static> = MTBRegister {
2125 addr : 0xe,
2126 mask : 0x2,
2127 descr : "Choose between the 2 tiu links",
2128 rmw : true,
2129 ro : false,
2130 pulse : false,
2131};
2132
2133///TRIG_GEN_RATE 0x9 0x24 \[31:0\] rw 0x0 Rate of generated triggers f_trig = (1/clk_period) * rate/0xffffffff
2134/// Set a random forced trigger
2135pub const TRIG_GEN_RATE : MTBRegister<'static> = MTBRegister {
2136 addr : 0x9,
2137 mask : 0xffffffff,
2138 descr : "Set a forced trigger (1/clk_period) * rate/0xffffffff",
2139 rmw : false,
2140 ro : false,
2141 pulse : false,
2142};
2143
2144// All the trigger settings
2145
2146// .... WIP!!! So many are not implemented yet....
2147
2148//LOOPBACK 0x0 0x0 [31:0] rw 0x0 Loopback register
2149//CLOCK_RATE 0x1 0x4 [31:0] r System clock frequency
2150//FB_CLOCK_RATE_0 0x2 0x8 [31:0] r Feedback clock frequency
2151//FB_CLOCK_RATE_1 0x3 0xc [31:0] r Feedback clock frequency
2152//FB_CLOCK_RATE_2 0x4 0x10 [31:0] r Feedback clock frequency
2153//FB_CLOCK_RATE_3 0x5 0x14 [31:0] r Feedback clock frequency
2154//FB_CLOCK_RATE_4 0x6 0x18 [31:0] r Feedback clock frequency
2155//DSI_ON 0x7 0x1c [4:0] rw 0x1F Bitmask 1 = enable DSI
2156//RESYNC 0xa 0x28 0 w Pulse Write 1 to resync
2157//ANY_TRIG_IS_GLOBAL 0xb 0x2c 0 rw 0x0 1 makes the ANY trigger read all paddles.
2158//TRACK_TRIG_IS_GLOBAL 0xb 0x2c 1 rw 0x0 1 makes the TRACK trigger read all paddles.
2159//TRACK_CENTRAL_IS_GLOBAL 0xb 0x2c 2 rw 0x0 1 makes the TRACK central read all paddles.
2160//TRACK_CENTRAL_IS_GLOBAL 0xb 0x2c 2 rw 0x0 1 makes the TRACK central read all paddles.
2161//TIU_EMU_BUSY_CNT 0xe 0x38 [31:14] rw 0xC350 Number of 10 ns clock cyles that the emulator will remain busy
2162//TIU_BAD 0xf 0x3c 0 r 1 means that the tiu link is not working
2163//LT_INPUT_STRETCH 0xf 0x3c [7:4] rw 0xF Number of clock cycles to stretch the LT inputs by
2164//MT.EVENT_QUEUE
2165//
2166//DAQ Buffer
2167//Node Adr Adr8 Bits Perm Def Description
2168//RESET 0x10 0x40 0 w Pulse DAQ Buffer Reset
2169//DATA 0x11 0x44 [31:0] r DAQ Read Data
2170//FULL 0x12 0x48 0 r DAQ Buffer Full
2171//EMPTY 0x12 0x48 1 r DAQ Buffer Empty
2172//SIZE 0x13 0x4c [31:16] r DAQ Buffer Head Event Size
2173//
2174//MT
2175//
2176//
2177//MT.HIT_COUNTERS
2178//
2179//Counters
2180//Node Adr Adr8 Bits Perm Def Description
2181//LT0 0x20 0x80 [23:0] r hit count on LT=0
2182//LT1 0x21 0x84 [23:0] r hit count on LT=1
2183//LT2 0x22 0x88 [23:0] r hit count on LT=2
2184//LT3 0x23 0x8c [23:0] r hit count on LT=3
2185//LT4 0x24 0x90 [23:0] r hit count on LT=4
2186//LT5 0x25 0x94 [23:0] r hit count on LT=5
2187//LT6 0x26 0x98 [23:0] r hit count on LT=6
2188//LT7 0x27 0x9c [23:0] r hit count on LT=7
2189//LT8 0x28 0xa0 [23:0] r hit count on LT=8
2190//LT9 0x29 0xa4 [23:0] r hit count on LT=9
2191//LT10 0x2a 0xa8 [23:0] r hit count on LT=10
2192//LT11 0x2b 0xac [23:0] r hit count on LT=11
2193//LT12 0x2c 0xb0 [23:0] r hit count on LT=12
2194//LT13 0x2d 0xb4 [23:0] r hit count on LT=13
2195//LT14 0x2e 0xb8 [23:0] r hit count on LT=14
2196//LT15 0x2f 0xbc [23:0] r hit count on LT=15
2197//LT16 0x30 0xc0 [23:0] r hit count on LT=16
2198//LT17 0x31 0xc4 [23:0] r hit count on LT=17
2199//LT18 0x32 0xc8 [23:0] r hit count on LT=18
2200//LT19 0x33 0xcc [23:0] r hit count on LT=19
2201//LT20 0x34 0xd0 [23:0] r hit count on LT=20
2202//LT21 0x35 0xd4 [23:0] r hit count on LT=21
2203//LT22 0x36 0xd8 [23:0] r hit count on LT=22
2204//LT23 0x37 0xdc [23:0] r hit count on LT=23
2205//LT24 0x38 0xe0 [23:0] r hit count on LT=24
2206//RESET 0x39 0xe4 0 w Pulse Write 1 to reset hit counters.
2207//SNAP 0x3a 0xe8 0 rw 0x1 1 to snap the hit counters.
2208//
2209//MT
2210//
2211//Implements various control and monitoring functions of the DRS Logic
2212//Node Adr Adr8 Bits Perm Def Description
2213//ETH_RX_BAD_FRAME_CNT 0x3d 0xf4 [15:0] r Ethernet MAC bad frame error
2214//ETH_RX_BAD_FCS_CNT 0x3d 0xf4 [31:16] r Ethernet MAC bad fcs
2215//
2216//MT.CHANNEL_MASK
2217//
2218//1 to mask a channel
2219//Node Adr Adr8 Bits Perm Def Description
2220//LT0 0x50 0x140 [7:0] rw 0x0 1 to mask a channel of LT=0
2221//LT1 0x51 0x144 [7:0] rw 0x0 1 to mask a channel of LT=1
2222//LT2 0x52 0x148 [7:0] rw 0x0 1 to mask a channel of LT=2
2223//LT3 0x53 0x14c [7:0] rw 0x0 1 to mask a channel of LT=3
2224//LT4 0x54 0x150 [7:0] rw 0x0 1 to mask a channel of LT=4
2225//LT5 0x55 0x154 [7:0] rw 0x0 1 to mask a channel of LT=5
2226//LT6 0x56 0x158 [7:0] rw 0x0 1 to mask a channel of LT=6
2227//LT7 0x57 0x15c [7:0] rw 0x0 1 to mask a channel of LT=7
2228//LT8 0x58 0x160 [7:0] rw 0x0 1 to mask a channel of LT=8
2229//LT9 0x59 0x164 [7:0] rw 0x0 1 to mask a channel of LT=9
2230//LT10 0x5a 0x168 [7:0] rw 0x0 1 to mask a channel of LT=10
2231//LT11 0x5b 0x16c [7:0] rw 0x0 1 to mask a channel of LT=11
2232//LT12 0x5c 0x170 [7:0] rw 0x0 1 to mask a channel of LT=12
2233//LT13 0x5d 0x174 [7:0] rw 0x0 1 to mask a channel of LT=13
2234//LT14 0x5e 0x178 [7:0] rw 0x0 1 to mask a channel of LT=14
2235//LT15 0x5f 0x17c [7:0] rw 0x0 1 to mask a channel of LT=15
2236//LT16 0x60 0x180 [7:0] rw 0x0 1 to mask a channel of LT=16
2237//LT17 0x61 0x184 [7:0] rw 0x0 1 to mask a channel of LT=17
2238//LT18 0x62 0x188 [7:0] rw 0x0 1 to mask a channel of LT=18
2239//LT19 0x63 0x18c [7:0] rw 0x0 1 to mask a channel of LT=19
2240//LT20 0x64 0x190 [7:0] rw 0x0 1 to mask a channel of LT=20
2241//LT21 0x65 0x194 [7:0] rw 0x0 1 to mask a channel of LT=21
2242//LT22 0x66 0x198 [7:0] rw 0x0 1 to mask a channel of LT=22
2243//LT23 0x67 0x19c [7:0] rw 0x0 1 to mask a channel of LT=23
2244//LT24 0x68 0x1a0 [7:0] rw 0x0 1 to mask a channel of LT=24
2245//
2246//MT.COARSE_DELAYS
2247//Node Adr Adr8 Bits Perm Def Description
2248//LT0 0xc0 0x300 [3:0] rw 0x0 Integer clock delay of LT LINK 0
2249//LT1 0xc1 0x304 [3:0] rw 0x0 Integer clock delay of LT LINK 1
2250//LT2 0xc2 0x308 [3:0] rw 0x0 Integer clock delay of LT LINK 2
2251//LT3 0xc3 0x30c [3:0] rw 0x0 Integer clock delay of LT LINK 3
2252//LT4 0xc4 0x310 [3:0] rw 0x0 Integer clock delay of LT LINK 4
2253//LT5 0xc5 0x314 [3:0] rw 0x0 Integer clock delay of LT LINK 5
2254//LT6 0xc6 0x318 [3:0] rw 0x0 Integer clock delay of LT LINK 6
2255//LT7 0xc7 0x31c [3:0] rw 0x0 Integer clock delay of LT LINK 7
2256//LT8 0xc8 0x320 [3:0] rw 0x0 Integer clock delay of LT LINK 8
2257//LT9 0xc9 0x324 [3:0] rw 0x0 Integer clock delay of LT LINK 9
2258//LT10 0xca 0x328 [3:0] rw 0x0 Integer clock delay of LT LINK 10
2259//LT11 0xcb 0x32c [3:0] rw 0x0 Integer clock delay of LT LINK 11
2260//LT12 0xcc 0x330 [3:0] rw 0x0 Integer clock delay of LT LINK 12
2261//LT13 0xcd 0x334 [3:0] rw 0x0 Integer clock delay of LT LINK 13
2262//LT14 0xce 0x338 [3:0] rw 0x0 Integer clock delay of LT LINK 14
2263//LT15 0xcf 0x33c [3:0] rw 0x0 Integer clock delay of LT LINK 15
2264//LT16 0xd0 0x340 [3:0] rw 0x0 Integer clock delay of LT LINK 16
2265//LT17 0xd1 0x344 [3:0] rw 0x0 Integer clock delay of LT LINK 17
2266//LT18 0xd2 0x348 [3:0] rw 0x0 Integer clock delay of LT LINK 18
2267//LT19 0xd3 0x34c [3:0] rw 0x0 Integer clock delay of LT LINK 19
2268//LT20 0xd4 0x350 [3:0] rw 0x0 Integer clock delay of LT LINK 20
2269//LT21 0xd5 0x354 [3:0] rw 0x0 Integer clock delay of LT LINK 21
2270//LT22 0xd6 0x358 [3:0] rw 0x0 Integer clock delay of LT LINK 22
2271//LT23 0xd7 0x35c [3:0] rw 0x0 Integer clock delay of LT LINK 23
2272//LT24 0xd8 0x360 [3:0] rw 0x0 Integer clock delay of LT LINK 24
2273//LT25 0xd9 0x364 [3:0] rw 0x0 Integer clock delay of LT LINK 25
2274//LT26 0xda 0x368 [3:0] rw 0x0 Integer clock delay of LT LINK 26
2275//LT27 0xdb 0x36c [3:0] rw 0x0 Integer clock delay of LT LINK 27
2276//LT28 0xdc 0x370 [3:0] rw 0x0 Integer clock delay of LT LINK 28
2277//LT29 0xdd 0x374 [3:0] rw 0x0 Integer clock delay of LT LINK 29
2278//LT30 0xde 0x378 [3:0] rw 0x0 Integer clock delay of LT LINK 30
2279//LT31 0xdf 0x37c [3:0] rw 0x0 Integer clock delay of LT LINK 31
2280//LT32 0xe0 0x380 [3:0] rw 0x0 Integer clock delay of LT LINK 32
2281//LT33 0xe1 0x384 [3:0] rw 0x0 Integer clock delay of LT LINK 33
2282//LT34 0xe2 0x388 [3:0] rw 0x0 Integer clock delay of LT LINK 34
2283//LT35 0xe3 0x38c [3:0] rw 0x0 Integer clock delay of LT LINK 35
2284//LT36 0xe4 0x390 [3:0] rw 0x0 Integer clock delay of LT LINK 36
2285//LT37 0xe5 0x394 [3:0] rw 0x0 Integer clock delay of LT LINK 37
2286//LT38 0xe6 0x398 [3:0] rw 0x0 Integer clock delay of LT LINK 38
2287//LT39 0xe7 0x39c [3:0] rw 0x0 Integer clock delay of LT LINK 39
2288//LT40 0xe8 0x3a0 [3:0] rw 0x0 Integer clock delay of LT LINK 40
2289//LT41 0xe9 0x3a4 [3:0] rw 0x0 Integer clock delay of LT LINK 41
2290//LT42 0xea 0x3a8 [3:0] rw 0x0 Integer clock delay of LT LINK 42
2291//LT43 0xeb 0x3ac [3:0] rw 0x0 Integer clock delay of LT LINK 43
2292//LT44 0xec 0x3b0 [3:0] rw 0x0 Integer clock delay of LT LINK 44
2293//LT45 0xed 0x3b4 [3:0] rw 0x0 Integer clock delay of LT LINK 45
2294//LT46 0xee 0x3b8 [3:0] rw 0x0 Integer clock delay of LT LINK 46
2295//LT47 0xef 0x3bc [3:0] rw 0x0 Integer clock delay of LT LINK 47
2296//LT48 0xf0 0x3c0 [3:0] rw 0x0 Integer clock delay of LT LINK 48
2297//LT49 0xf1 0x3c4 [3:0] rw 0x0 Integer clock delay of LT LINK 49
2298//
2299//MT.RB_READOUT_CNTS
2300//
2301//Counters
2302//Node Adr Adr8 Bits Perm Def Description
2303//CNTS_0 0xf2 0x3c8 [7:0] r Readout count on RB=0
2304//CNTS_1 0xf2 0x3c8 [15:8] r Readout count on RB=1
2305//CNTS_2 0xf2 0x3c8 [23:16] r Readout count on RB=2
2306//CNTS_3 0xf2 0x3c8 [31:24] r Readout count on RB=3
2307//CNTS_4 0xf3 0x3cc [7:0] r Readout count on RB=4
2308//CNTS_5 0xf3 0x3cc [15:8] r Readout count on RB=5
2309//CNTS_6 0xf3 0x3cc [23:16] r Readout count on RB=6
2310//CNTS_7 0xf3 0x3cc [31:24] r Readout count on RB=7
2311//CNTS_8 0xf4 0x3d0 [7:0] r Readout count on RB=8
2312//CNTS_9 0xf4 0x3d0 [15:8] r Readout count on RB=9
2313//CNTS_10 0xf4 0x3d0 [23:16] r Readout count on RB=10
2314//CNTS_11 0xf4 0x3d0 [31:24] r Readout count on RB=11
2315//CNTS_12 0xf5 0x3d4 [7:0] r Readout count on RB=12
2316//CNTS_13 0xf5 0x3d4 [15:8] r Readout count on RB=13
2317//CNTS_14 0xf5 0x3d4 [23:16] r Readout count on RB=14
2318//CNTS_15 0xf5 0x3d4 [31:24] r Readout count on RB=15
2319//CNTS_16 0xf6 0x3d8 [7:0] r Readout count on RB=16
2320//CNTS_17 0xf6 0x3d8 [15:8] r Readout count on RB=17
2321//CNTS_18 0xf6 0x3d8 [23:16] r Readout count on RB=18
2322//CNTS_19 0xf6 0x3d8 [31:24] r Readout count on RB=19
2323//CNTS_20 0xf7 0x3dc [7:0] r Readout count on RB=20
2324//CNTS_21 0xf7 0x3dc [15:8] r Readout count on RB=21
2325//CNTS_22 0xf7 0x3dc [23:16] r Readout count on RB=22
2326//CNTS_23 0xf7 0x3dc [31:24] r Readout count on RB=23
2327//CNTS_24 0xf8 0x3e0 [7:0] r Readout count on RB=24
2328//CNTS_25 0xf8 0x3e0 [15:8] r Readout count on RB=25
2329//CNTS_26 0xf8 0x3e0 [23:16] r Readout count on RB=26
2330//CNTS_27 0xf8 0x3e0 [31:24] r Readout count on RB=27
2331//CNTS_28 0xf9 0x3e4 [7:0] r Readout count on RB=28
2332//CNTS_29 0xf9 0x3e4 [15:8] r Readout count on RB=29
2333//CNTS_30 0xf9 0x3e4 [23:16] r Readout count on RB=30
2334//CNTS_31 0xf9 0x3e4 [31:24] r Readout count on RB=31
2335//CNTS_32 0xfa 0x3e8 [7:0] r Readout count on RB=32
2336//CNTS_33 0xfa 0x3e8 [15:8] r Readout count on RB=33
2337//CNTS_34 0xfa 0x3e8 [23:16] r Readout count on RB=34
2338//CNTS_35 0xfa 0x3e8 [31:24] r Readout count on RB=35
2339//CNTS_36 0xfb 0x3ec [7:0] r Readout count on RB=36
2340//CNTS_37 0xfb 0x3ec [15:8] r Readout count on RB=37
2341//CNTS_38 0xfb 0x3ec [23:16] r Readout count on RB=38
2342//CNTS_39 0xfb 0x3ec [31:24] r Readout count on RB=39
2343//CNTS_40 0xfc 0x3f0 [7:0] r Readout count on RB=40
2344//CNTS_41 0xfc 0x3f0 [15:8] r Readout count on RB=41
2345//CNTS_42 0xfc 0x3f0 [23:16] r Readout count on RB=42
2346//CNTS_43 0xfc 0x3f0 [31:24] r Readout count on RB=43
2347//CNTS_44 0xfd 0x3f4 [7:0] r Readout count on RB=44
2348//CNTS_45 0xfd 0x3f4 [15:8] r Readout count on RB=45
2349//CNTS_46 0xfd 0x3f4 [23:16] r Readout count on RB=46
2350//CNTS_47 0xfd 0x3f4 [31:24] r Readout count on RB=47
2351//CNTS_48 0xfe 0x3f8 [7:0] r Readout count on RB=48
2352//CNTS_49 0xfe 0x3f8 [15:8] r Readout count on RB=49
2353//RESET 0xff 0x3fc 0 w Pulse Write 1 to reset hit counters.
2354//SNAP 0x100 0x400 0 rw 0x1 1 to snap the hit counters.
2355//
2356//MT.PULSER
2357//
2358//LTB Channel Pulser
2359//Node Adr Adr8 Bits Perm Def Description
2360//FIRE 0x100 0x400 0 w Pulse Write 1 to Fire the Pulser.
2361//CH_0_24 0x101 0x404 [24:0] rw 0x0 Set fire bits for channels 0 to 24
2362//CH_25_49 0x102 0x408 [24:0] rw 0x0 Set fire bits for channels 25 to 49
2363//CH_50_74 0x103 0x40c [24:0] rw 0x0 Set fire bits for channels 50 to 74
2364//CH_75_99 0x104 0x410 [24:0] rw 0x0 Set fire bits for channels 75 to 99
2365//CH_100_124 0x105 0x414 [24:0] rw 0x0 Set fire bits for channels 100 to 124
2366//CH_125_149 0x106 0x418 [24:0] rw 0x0 Set fire bits for channels 125 to 149
2367//CH_150_174 0x107 0x41c [24:0] rw 0x0 Set fire bits for channels 150 to 174
2368//CH_175_199 0x108 0x420 [24:0] rw 0x0 Set fire bits for channels 175 to 199
2369//
2370//MT.XADC
2371//
2372//Zynq XADC
2373//Node Adr Adr8 Bits Perm Def Description
2374//CALIBRATION 0x120 0x480 [11:0] r XADC Calibration
2375//VCCPINT 0x120 0x480 [27:16] r XADC vccpint
2376//VCCPAUX 0x121 0x484 [11:0] r XADC Calibration
2377//VCCODDR 0x121 0x484 [27:16] r XADC vccoddr
2378//TEMP 0x122 0x488 [11:0] r XADC Temperature
2379//VCCINT 0x122 0x488 [27:16] r XADC vccint
2380//VCCAUX 0x123 0x48c [11:0] r XADC VCCAUX
2381//VCCBRAM 0x123 0x48c [27:16] r XADC vccbram
2382//
2383//MT.HOG
2384//
2385//HOG Parameters
2386//Node Adr Adr8 Bits Perm Def Description
2387//GLOBAL_DATE 0x200 0x800 [31:0] r HOG Global Date
2388//GLOBAL_TIME 0x201 0x804 [31:0] r HOG Global Time
2389//GLOBAL_VER 0x202 0x808 [31:0] r HOG Global Version
2390//GLOBAL_SHA 0x203 0x80c [31:0] r HOG Global SHA
2391//TOP_SHA 0x204 0x810 [31:0] r HOG Top SHA
2392//TOP_VER 0x205 0x814 [31:0] r HOG Top Version
2393//HOG_SHA 0x206 0x818 [31:0] r HOG SHA
2394//HOG_VER 0x207 0x81c [31:0] r HOG Version
2395//Module SPI adr = 0x1000
2396//
2397//SPI
2398//Node Adr Adr8 Bits Perm Def Description
2399//d0 0x1000 0x4000 [31:0] rw ~~ Data reg 0
2400//d1 0x1001 0x4004 [31:0] rw ~~ Data reg 1
2401//d2 0x1002 0x4008 [31:0] rw ~~ Data reg 2
2402//d3 0x1003 0x400c [31:0] rw ~~ Data reg 3
2403//ctrl 0x1004 0x4010 [31:0] rw ~~ Control reg
2404//divider 0x1005 0x4014 [31:0] rw ~~ Clock divider reg
2405//ss 0x1006 0x4018 [31:0] rw ~~ Slave select reg
2406//Module I2C adr = 0x1100
2407//
2408//I2C master controller
2409//
2410//I2C
2411//
2412//I2C master controller
2413//Node Adr Adr8 Bits Perm Def Description
2414//ps_lo 0x1100 0x4400 [7:0] rw ~~ Prescale low byte
2415//ps_hi 0x1101 0x4404 [7:0] rw ~~ Prescale low byte
2416//ctrl 0x1102 0x4408 [7:0] rw ~~ Control
2417//data 0x1103 0x440c [7:0] rw ~~ Data
2418//cmd_stat 0x1104 0x4410 [7:0] rw ~~ Command / status
2419
2420
2421